DRAM Memory Test Method for Row Hammer Attack Resistance Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory test methods are insufficient in verifying the attack resistance capability of DRAM against flexible and improved attack scenarios, leading to unreliable results and high success rates of attacks, as they fail to comprehensively test the memory's ability to resist row hammer effects.
Innovation Solution
A memory test method that determines a refresh cycle, attack resistance frequency, and single row read time to calculate the number of target attack rows, which are then read consecutively to detect data exceptions in adjacent rows, performing multiple tests within refresh cycles to assess the memory's attack resistance capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a small quantity of protection programs are set for memories, then the device complexity is reduced, but the reliability of attack resistance verification deteriorates
Solution Approach 1:
The patent changes the parameter of attack row quantity from fixed/small to dynamically determined based on refresh cycle, attack resistance frequency, and single row read time. This allows comprehensive verification without requiring multiple protection programs, resolving the contradiction between device complexity and verification reliability.
2Productivity
If multiple attack tests are performed within refresh cycles, then the productivity of memory testing is improved, but the difficulty of detecting and measuring increases
Solution Approach 1:
The patent segments the memory into multiple target attack rows (N rows spaced apart by one row) and performs parallel attack tests on different row groups within refresh cycles. This segmentation enables high-speed testing while maintaining detectability through structured row selection and monitoring.
Solution Approach 2:
The patent implements periodic attack tests within refresh cycles, performing MT/NXt tests systematically. This periodic structure maintains testing productivity while simplifying detection through regular, predictable test patterns that are easier to monitor and evaluate.
3Measurement precision
If N target attack rows are read for X consecutive times, then the measurement precision of attack resistance is improved, but the loss of time increases
Solution Approach 1:
The patent performs preliminary calculation of attack row quantity N based on refresh cycle T, attack resistance frequency F, and single row read time t before executing tests. This preliminary action ensures that the subsequent X consecutive reads achieve necessary measurement precision while minimizing time loss by optimizing the test parameters in advance.
Data Source
AI summary
The present disclosure provides a memory test method. The method includes: determining a refresh cycle T, a designed attack resistance frequency F, and a single row read time t of a target repository; determining an attack row quantity N based on the refresh cycle T, the designed attack resistance frequency F, and the single row read time t; determining a group of target attack rows in the target repository based on a value of the attack row quantity N, where the group of target attack rows include N target attack rows, and at least two of the N target attack rows are spaced apart by one row; detecting, after reading the N target attack rows for X consecutive times, whether data exception occurs in all adjacent rows of the target attack rows, to complete one attack test.