DRAM Row Hammering Mitigation via Logical Block Access Control

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Solution Overview

Problem

Dynamic random-access memory (DRAM) experiences data corruption or loss due to repetitive accesses without refresh, known as 'row hammering', which existing solutions address by increasing refresh frequency or reducing bandwidth, leading to performance penalties.

Innovation Solution

Divide DRAM banks into logical blocks, map rows to these blocks, and monitor accesses using counters to enforce throttling when access thresholds are exceeded, thereby preventing data corruption without significantly reducing bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh frequency is increased to prevent row hammering, then data reliability is improved, but memory bandwidth is reduced

Engineering Contradiction:

Improvedata reliabilityVSAvoidmemory bandwidth

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent divides the DRAM bank into multiple logical blocks (e.g., 4 logical blocks) and further segments the monitoring function by tracking access counts per logical block rather than per individual row. This segmentation allows the system to manage refresh requirements at a coarser granularity, reducing unnecessary refresh operations while maintaining data reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic monitoring and control by tracking access counts in real-time and adjusting refresh behavior based on actual access patterns. The system dynamically determines when a logical block needs refreshing based on its access count, rather than using fixed refresh intervals for all rows, thereby optimizing the balance between reliability and bandwidth.

Inventive Principle:

Principle #15Dynamics

2Reliability

If access throttling is applied to prevent row hammering, then data reliability is improved, but access speed is reduced

Engineering Contradiction:

Improvedata reliabilityVSAvoidaccess speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent applies local quality by treating different logical blocks differently based on their access patterns. Instead of uniformly throttling all accesses, the system identifies specific logical blocks that exceed access thresholds and applies throttling only to those, while allowing normal access speed to other blocks. This localized approach maintains overall access speed while preventing row hammering in affected areas.

Inventive Principle:

Principle #3Local quality

3Productivity

If refresh intervals are extended to improve memory efficiency, then bandwidth is improved, but risk of data corruption increases

Engineering Contradiction:

Improvememory efficiencyVSAvoiddata integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements feedback by continuously monitoring access counts for each logical block and using this information to determine when refreshing is necessary. The system compares actual access patterns against safety thresholds and adjusts refresh timing accordingly, allowing extended intervals when safe while maintaining data integrity through real-time feedback control.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9478263B2Systems and methods for monitoring and controlling repetitive accesses to volatile memory

Publication Date: 2016.10.25 APPLE INC

AI summary

Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.