DRAM Signal Sampling Phase Delay Circuit Skew Compensation
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Solution Overview
Problem
In DRAM memory systems, the varying lengths of conducting lines on circuit boards cause skew between data signals, leading to insufficient valid time and timing margin in the data valid window, especially when data transmission speed increases, making it challenging to properly sample data.
Innovation Solution
A signal sampling apparatus and method that includes a phase delay circuit to delay data signals by a predetermined time, generating a delayed signal, which is then sampled using a data sampling circuit, ensuring that rising and falling edges of the data strobe signal occur within the valid time of each data signal, thereby maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased, then productivity is improved, but the valid time and timing margin of the data valid window become insufficient
Solution Approach 1:
The patent applies dynamics by making the data valid window adjustable rather than fixed. The memory controller dynamically extends the data valid window for data signals with shorter valid times (due to line skew) while maintaining the original window for signals with adequate valid times. This dynamic adjustment allows the system to accommodate varying signal arrival times without reducing data transmission speed, thus resolving the contradiction between productivity and valid time sufficiency.
Solution Approach 2:
The patent changes the parameter of the data valid window duration based on the specific data signal being transmitted. By detecting the valid time of each data signal and selectively extending the data valid window only when necessary (when the detected valid time is shorter than a threshold), the system optimizes the timing margin for high-speed transmission without unnecessarily extending windows for all signals, thereby maintaining high productivity while ensuring adequate sampling time.
2Ease of manufacture
If conducting lines have different lengths, then ease of manufacture is improved, but skew occurs between data signals resulting in insufficient timing margin
Solution Approach 1:
The patent implements feedback by having the memory controller detect the actual valid time of each data signal received from the memory device. Based on this feedback information, the controller determines whether the data valid window needs to be extended for each specific signal. This feedback mechanism allows the system to compensate for skew caused by different line lengths without requiring precise manufacturing control, thus resolving the contradiction between manufacturing ease and timing precision.
Data Source
AI summary
A signal sampling apparatus for a DRAM memory comprises a phase delay circuit adapted for receiving a data signal and delaying the data signal by a predetermined time to generate a delay signal; and a sampling circuit for sampling the data signal according to the delay signal.