DRAM Sense Amplifier Overdrive Control Circuit
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Solution Overview
Problem
The existing overdrive system in semiconductor memory faces challenges in accurately setting the end timing of the overdrive period, leading to issues with breakdown voltage and wasteful current consumption due to variations in VDD voltage, transistor characteristics, temperature, wiring resistance, and bitline capacitance, which affect the sensing speed and efficiency.
Innovation Solution
A semiconductor memory system with a first switch device connecting sense amplifiers to a power supply during overdrive, a capacitive device accumulating charges, and a control circuit to turn off the switches when the capacitive device reaches a preset voltage, followed by a third switch device supplying a second power supply to the sense amplifiers, allowing precise control of electrical charges and bitline potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the array voltage is lowered to cope with reduced breakdown voltage of memory cell elements, then the reliability is improved, but the sensing speed deteriorates
Solution Approach 1:
The patent applies dynamic voltage switching by implementing an overdrive circuit that temporarily supplies a higher voltage (VDD1) to the sense amplifier during the sensing operation, then switches to the lower voltage (VDD2) for subsequent operations. This dynamic voltage adjustment allows the system to achieve both high reliability through reduced breakdown voltage and high sensing speed through temporary voltage boosting.
Solution Approach 2:
The patent implements periodic overdrive signaling where the overdrive circuit activates at specific intervals during sensing operations. The overdrive signal is generated periodically to boost the sense amplifier voltage only when needed, allowing the system to maintain low power consumption and high reliability while achieving high sensing speed during critical operation windows.
2Speed
If the overdrive period is extended to improve sensing speed, then the sensing speed is improved, but the current consumption increases
Solution Approach 1:
The patent dynamically controls the duration of the overdrive period by using a delay circuit that generates an overdrive signal with a precisely controlled time width. The overdrive circuit switches voltages based on this time-controlled signal, allowing the system to optimize sensing speed while minimizing current consumption by limiting the overdrive duration to only what is necessary.
Solution Approach 2:
The patent employs a delay circuit that monitors the sensing operation progress and generates an overdrive signal that automatically terminates when the sensing is complete. This feedback mechanism ensures the overdrive period is extended only as long as needed to complete the sensing operation, preventing excessive current consumption while maintaining adequate sensing speed.
3Reliability
If the overdrive timing is delayed to wait for bitline potential stabilization, then the reliability is improved, but the sensing speed deteriorates
Solution Approach 1:
The patent applies preliminary action by generating the overdrive signal in advance of the actual sensing operation. The delay circuit is configured to produce the overdrive signal before the bitline potential fully stabilizes, allowing the sense amplifier to begin its amplification process earlier. This preliminary voltage boosting enables the system to achieve both reliable bitline potential stabilization and high sensing speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables accurate control of electrical charges during the overdrive period, ensuring the bitline potential is set to the desired array voltage, thereby optimizing sensing speed and reducing current consumption and layout area.
Implementation Method 1
a capacitive device for accumulating electrical charges referenced to in association with electrical charges supplied via the first switch device to the sense amplifiers
Data Source
AI summary
A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP1, capacitor C1, MOS transistor TP2, and control circuit. MOS transistor TP1 is turned on when overdriving begins, and is designed to supply voltage of power supply VDD1 to parallel-connected sense amplifiers. Capacitor C1 accumulates electrical charges referenced to in association with electrical charges supplied to sense the amplifiers via MOS transistor TP1. MOS transistor TP2 is turned on when overdriving begins, to supply voltage of power supply VDD1 to capacitor C1. The control circuit controls so that MOS transistors TP1, TP2 are turned off when the capacitor potential has reached voltage VREF1. There is also provided a MOS transistor turned on after the MOS transistors TP1, TP2 are turned off to supply a power supply voltage equal to the voltage VREF1 to the plural sense amplifiers.