DRAM Reference Cell Series Capacitor Noise Reduction
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Solution Overview
Problem
Conventional DRAM circuits face challenges in providing a stable, high current reference voltage for sensing operations, especially at increased frequencies, leading to noise and degraded memory performance due to the requirement of a unique reference cell with a capacitor identical to the memory cell.
Innovation Solution
A DRAM circuit design featuring a memory cell with a single trench capacitor and a reference cell comprising two trench capacitors connected in series, providing half the capacitance of the memory cell, which can be formed using the same fabrication processes, eliminating the need for a specific reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional reference cell with a single capacitor identical to the memory cell capacitor is used, then the reference cell can provide a reference voltage for sensing, but it requires a particular reference voltage (VREF) that becomes unstable and noisy at high frequencies
Solution Approach 1:
The reference cell capacitor is segmented into two identical trench capacitors connected in series. Each capacitor has half the capacitance of the original single capacitor, and when connected in series, they provide the required reference function without requiring an unstable high-current VREF supply, thereby reducing noise and improving reliability at high frequencies.
Solution Approach 2:
The capacitance parameter of the reference cell is changed from a single large capacitor to two smaller capacitors in series. This parameter change allows the reference cell to operate without requiring a high-current reference voltage supply, eliminating the noise and instability issues that occur at high frequencies while maintaining the necessary reference function.
2Device complexity
If a reference cell with a single capacitor identical to the memory cell capacitor is used, then the capacitor structure can be simple, but the reference voltage supply becomes complex and difficult to maintain at high frequencies
Solution Approach 1:
The reference cell capacitor is divided into two identical trench capacitors connected in series. This segmentation simplifies the voltage supply requirements because each smaller capacitor can be charged to a lower voltage, eliminating the need for a complex high-current VREF supply while maintaining compatibility with standard memory cell structures.
Solution Approach 2:
Instead of using a single large capacitor that requires a complex high-current voltage supply, the invention inverts the approach by using two smaller capacitors in series that can operate with simpler voltage requirements, thereby improving high-frequency operation capability while reducing supply complexity.
3Object-affected harmful factors
If two trench capacitors are used in the reference cell, then the capacitance can be halved to reduce noise, but the fabrication process becomes more complex
Solution Approach 1:
The capacitance parameter is changed by using two smaller capacitors in series instead of one large capacitor. This parameter change reduces noise while maintaining ease of manufacture because the two smaller capacitors can be formed using the same trench capacitor fabrication processes already established for memory cells, requiring only minor process adjustments.
Solution Approach 2:
The trench capacitor structure is made universal by designing it to serve both as memory cell capacitors and reference cell capacitors. The same fabrication processes form both types of capacitors, allowing the reference cell to use two identical trench capacitors without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces noise and enhances memory performance by allowing the reference cell to operate without a particular reference voltage, maintaining stability and high current supply, thus improving sensing operations.
Implementation Method 1
The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor
Implementation Method 2
Each trench capacitor can further comprise a buried capacitor plate within the semiconductor substrate adjacent the trench, a capacitor dielectric layer lining the trench and, a additional capacitor plate on the capacitor dielectric layer within the trench
Data Source
AI summary
Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.