DRAM Structure with Shared Counter Electrode
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Solution Overview
Problem
The performance gap between logic/SOC chips and DRAM chips is exacerbated by the slower scaling rate of DRAM technology compared to logic technology, primarily due to the lack of a suitable DRAM cell structure compatible with leading logic processes, particularly with FinFET transistors, and the difficulty in scaling down deep-trench capacitor cell structures.
Innovation Solution
A DRAM structure featuring a concave capacitor set with a shared counter electrode, fin-structured transistors, and an isolating layer, where the capacitor set is formed in a concave semiconductor substrate with collar connectors and a high dielectric constant insulator, allowing for improved compatibility with FinFET transistors and enhanced capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep-trench capacitor cell structure is used, then capacitance is improved, but scaling below 14 nanometers becomes difficult
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional stacked capacitor structures. Multiple capacitor stacks are vertically arranged within a single memory cell, utilizing the vertical dimension to increase capacitance without reducing lateral feature size. This allows the cell to achieve higher capacitance values while maintaining compatibility with advanced nanometer-scale processing nodes.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor elements are stacked within each other vertically. Each capacitor stack contains multiple dielectric layers and electrode layers arranged in a nested configuration, maximizing the use of vertical space to achieve high capacitance in a compact footprint suitable for sub-14nm technology nodes.
2Length of moving object
If stacked-capacitor cell structure is used, then feature size is reduced, but further scaling below 15-12 nanometers becomes difficult
Solution Approach 1:
The patent continues to exploit the vertical dimension by increasing the number of stacks per cell and the height of individual capacitor stacks. This allows further reduction of lateral feature size while compensating for reduced capacitance per stack through increased vertical capacity and parallel stack arrangements.
Solution Approach 2:
The patent segments the capacitor structure into multiple independent stacks that can be individually optimized. Each stack is a separate capacitive element, allowing the overall cell capacitance to be achieved through the parallel combination of multiple segmented stacks, thereby enabling further scaling while maintaining total capacitance.
3Productivity
If FinFET transistor structure is adopted, then logic chip performance is improved, but DRAM compatibility and scaling become challenging
Solution Approach 1:
The patent develops a universal memory cell structure that is compatible with both FinFET transistors used in logic chips and the capacitor structures needed for DRAM functionality. The stacked capacitor design can be integrated alongside FinFET access transistors, creating a unified structure that maintains high-performance logic compatibility while enabling DRAM operation at advanced technology nodes.
Solution Approach 2:
The patent applies different structural optimizations to different parts of the memory cell. The transistor region uses FinFET structures for high-performance switching, while the capacitor region uses stacked three-dimensional structures for high capacitance density. This local differentiation allows each component to be optimized for its specific function while maintaining overall compatibility with advanced logic processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the DRAM structure to match the operational speed of silicon logic circuits and maintain compatibility with current logic processes, reducing leakage and improving data retention while allowing for further scaling, thus bridging the performance gap between logic and DRAM chips.
Implementation Method 1
an insulator with a high dielectric constant positioned between the first electrode and the second electrode
Data Source
AI summary
The invention relates to a DRAM structure which comprise a capacitor set and at least a transistor. The capacitor set includes a first capacitor with a first electrode and a second capacitor with a second electrode, and a counter electrode is shared by the first and the second capacitors. The counter electrode is perpendicular or substantially perpendicular to an extension direction of an active region of the transistor, or the counter electrode is not positioned above or below the first and second electrode.