DRAM Spacer Layer Etch Stop for Gate Protection
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Solution Overview
Problem
The integration of MOS transistors in dynamic random access memory (DRAM) devices poses challenges due to varying structural designs across different regions on the same chip, leading to increased process complexity and potential damage from etching processes.
Innovation Solution
A method is developed to form a spacer layer that covers bit lines and a gate, using it as an etch stop layer to prevent damage during subsequent etching processes, resulting in an asymmetrical spacer structure that protects underlying elements and optimizes device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etching process is used for the entire chip, then the etching process is simple and fast, but the components in the substrate are damaged due to over-etching
Solution Approach 1:
The patent divides the chip into different regions (memory cell region and periphery region) and applies different etching processes to each region. The spacer layer is selectively formed in the periphery region to create a protected zone, allowing the etching process to be segmented into protected and unprotected areas, thus preventing over-etching damage while maintaining efficiency.
Solution Approach 2:
The spacer layer acts as an intermediary protective element between the etching process and the underlying components in the periphery region. This intermediate layer prevents direct contact between the etching chemicals and the sensitive components, thereby protecting them from damage while allowing the etching process to proceed efficiently in other regions.
2Adaptability or versatility
If different MOS transistor structures are used in different regions, then device performance is optimized, but process complexity increases
Solution Approach 1:
The patent applies local quality by forming the spacer layer specifically in the periphery region where different transistor structures are needed, while leaving the memory cell region unchanged. This localized modification allows different MOS transistor structures to be implemented in specific areas without requiring complex process changes across the entire chip, thus optimizing device performance while controlling process complexity.
Solution Approach 2:
The spacer layer is formed in advance before the etching process, preparing the periphery region for subsequent selective etching. This preliminary action enables the differentiation of regions and facilitates the formation of different MOS transistor structures without adding significant complexity to the overall manufacturing process.
3Manufacturing precision
If the etching process continues without an etch stop layer, then the etching is complete and thorough, but the underlying components are damaged
Solution Approach 1:
The spacer layer is formed in advance as an etch stop layer in the periphery region, creating a predetermined barrier before the etching process begins. This preliminary action ensures that when the etching process reaches the spacer layer, it automatically stops, preventing over-etching and damage to underlying components while maintaining complete etching in regions without the spacer layer.
Solution Approach 2:
The spacer layer serves as an intermediary etch stop layer that mediates between the etching process and the underlying components. It allows the etching to proceed thoroughly where needed while providing a controlled stopping point in the periphery region, thus eliminating the harmful effect of over-etching without compromising etching completeness in other areas.
Data Source
AI summary
A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery. The spacer layer covers the bit lines and a sidewall of the gate. The first spacer is disposed at two sides of the gate, covers on the spacer layer.