DRAM Stacked Capacitor Structure for High Integration Density
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Solution Overview
Problem
The miniaturization of DRAM devices leads to reduced cell area, making it difficult to maintain sufficient capacitance and signal-to-noise ratio, and the integration of memory and logic devices causes process issues due to differing device densities.
Innovation Solution
The formation of semiconductor devices with specific connecting structures, including conductive and metal portions of different heights, and the creation of dummy and storage nodes to increase pattern density and address the process issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are miniaturized to increase integration density, then the number of memory cells per device increases, but the cell area decreases making it difficult to maintain sufficient capacitance and signal-to-noise ratio
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional stacked capacitor structures. The storage capacitor is formed vertically over the access transistor, utilizing the vertical dimension to increase capacitance without occupying additional planar area. This stacked configuration allows sufficient capacitance to be maintained even as cell area is reduced through miniaturization.
Solution Approach 2:
The storage capacitor is nested over the access transistor structure, with the capacitor occupying the vertical space above the transistor. This nesting arrangement allows both the transistor and capacitor to share the same footprint area, maximizing space utilization and maintaining sufficient capacitance in miniaturized cells.
2Productivity
If memory cells are miniaturized to increase integration density, then more memory cells can be fitted on the device, but the fabrication difficulty increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the access transistor structure first, then forming the storage capacitor structure separately, and finally establishing the bit line and word line connections. This segmentation allows each component to be optimized independently while maintaining compatibility with miniaturized dimensions.
Solution Approach 2:
The access transistor structure is formed preliminarily before the storage capacitor is constructed. This preliminary action establishes a stable foundation that guides subsequent capacitor formation, ensuring proper alignment and electrical connections while facilitating the miniaturization process.
3Adaptability or versatility
If both memory cells and logic devices are integrated on the same substrate, then device functionality increases, but process issues arise due to differing device densities
Solution Approach 1:
The patent applies different structural configurations to different regions of the substrate. Memory cells utilize the stacked capacitor structure optimized for high-density storage, while logic devices in peripheral regions can employ different structures optimized for their specific functional requirements. This local quality approach allows each region to be optimized for its purpose while maintaining process compatibility across the entire substrate.
Data Source
AI summary
A method for forming a semiconductor device includes providing a substrate having a plurality of memory cells formed therein; forming an insulating layer on the substrate; forming a plurality of openings in the insulating layer and exposing a portion of the memory cells; forming a conductive portion and a metal layer in the openings; removing a portion of the metal layer to form a plurality of first metal portions and a plurality of second metal portions that the first metal portion and the conductive portion form a first connecting structure, and the second metal portion and the conductive portion form a second connecting structure; forming a passivation layer on the first connecting structures; and forming a plurality of first storage nodes and dummy nodes on the substrate and the first storage nodes and the dummy nodes are electrically connected to the second connecting structures and the first connecting structures respectively.