DRAM Sub-Bank Refresh Control Circuit
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Solution Overview
Problem
In volatile memory devices like DRAM, frequent refresh operations are necessary to prevent information decay, but these operations can interfere with access operations, reducing overall efficiency.
Innovation Solution
The memory array is divided into sub-banks, where refresh operations are performed on one sub-bank during access to another, using a refresh control circuit to manage refresh flags and counters to optimize refresh timing and prevent over-refreshing, allowing refreshes to occur concurrently with access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed periodically on the entire memory array, then information decay is prevented, but access operations are interrupted and overall efficiency decreases
Solution Approach 1:
The memory array is divided into multiple sub-banks, each with independent refresh control. This segmentation allows different sub-banks to operate independently - some performing refresh while others handle access operations, thereby preventing complete access interruption while maintaining information retention across the entire array.
Solution Approach 2:
By enabling refresh operations to occur concurrently with access operations in different sub-banks, the system maintains continuous useful action across the memory array. The parallel operation ensures that refresh operations do not create idle periods in the overall system, as access operations continue in other sub-banks during the refresh intervals.
2Productivity
If refresh operations are performed on the same sub-bank during access operations, then refresh and access can occur simultaneously, but over-refreshing may occur wasting time and resources
Solution Approach 1:
A refresh counter is implemented for each sub-bank that tracks the number of refresh operations performed. The refresh control circuit monitors this counter and compares it against a threshold value, enabling feedback-based control. When the counter reaches the threshold, further refresh operations are prevented, thereby avoiding over-refreshing and the associated time waste while maintaining optimal refresh frequency for information retention.
3Reliability
If separate refresh control circuits are implemented for each sub-bank, then precise refresh management is achieved, but device complexity increases
Solution Approach 1:
The refresh control circuit is designed with a homogeneous modular structure where each sub-bank receives identical control signals and uses the same refresh counter logic. This homogeneity simplifies the overall design by repeating a standardized control unit across multiple sub-banks, reducing the complexity that would arise from implementing entirely independent and potentially different control circuits for each sub-bank.
Data Source
AI summary
Apparatuses, systems, and methods for access based refresh operations. A memory bank may be divided into multiple sub-banks, each of which has a refresh control circuit. A word line in a first sub-bank may be refreshed responsive to a word line in a second sub-bank being accessed. Once a threshold number of refreshes have been performed in the sub-bank, further accesses to the other sub-banks may be ignored. If the threshold has not been met at the end of a refresh period, then the refresh control circuit may issue a refresh signal.