DRAM Cell Sustaining Voltage for Retention Time
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Solution Overview
Problem
Conventional DRAM cell access transistors face a trade-off between high reliability and performance due to high threshold voltage and thick gate dielectric requirements, leading to longer write times and signal loss, especially under high voltage stress.
Innovation Solution
The introduction of a sustaining voltage generator that produces a higher voltage level than signal ONE, stored in the DRAM cell before the access transistor is turned off, allowing for extended retention time and reduced leakage current through the access transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If the access transistor is designed with high threshold voltage to reduce leakage current, then the retention time is improved, but the write performance deteriorates due to longer write times
Solution Approach 1:
The patent applies preliminary action by bootstrapping the word line voltage before the access transistor needs to write data. The word line is pre-charged to a high voltage level (VPP) in advance, so when the access transistor turns on, it immediately receives the full voltage boost needed for fast writing, eliminating the delay that would otherwise occur while charging the transistor gate.
Solution Approach 2:
The patent implements dynamics by making the word line voltage variable rather than fixed. The word line voltage dynamically switches between normal operating voltage and a boosted VPP voltage level depending on whether the access transistor needs to be activated for writing. This dynamic voltage adjustment allows the transistor to achieve both low leakage (at normal voltage) and high write speed (at boosted voltage).
2Reliability
If the gate dielectric material is made thicker to sustain high word-line voltage, then the reliability is improved, but the transistor performance deteriorates
Solution Approach 1:
The patent applies local quality by providing different voltage levels to different parts of the circuit at different times. The word line receives high voltage (VPP) only when needed for writing operations, while the access transistor gate experiences this high voltage only during the brief window when the transistor is actually conducting. This localized, time-dependent high voltage exposure allows the dielectric to be thinner without compromising reliability, since it only experiences high stress during brief intervals rather than continuously.
Data Source
AI summary
The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.