DRAM Test Key Structures Fabricated Concurrently with Chip Arrays
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Solution Overview
Problem
Conventional test structures for dynamic random access memory devices face limitations in miniaturization and accuracy, requiring complex manufacturing processes and prone to unexpected changes, which complicates resistance measurements.
Innovation Solution
A method and structure for manufacturing test structures on semiconductor wafers, featuring a chain contact structure with MOS devices and landing plug structures, allowing for resistance measurements between contact structures, compatible with conventional processes and equipment, and designed for 0.13 microns and less design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional test structures are used for resistance measurement, then measurement capability is provided, but manufacturing complexity increases and miniaturization becomes difficult
Solution Approach 1:
The patent merges the test structure fabrication with the main IC chip fabrication process by forming test structures, contact structures, and interlayer dielectric layers concurrently with the chip structures using the same processes. This integration eliminates separate manufacturing steps, reducing overall process complexity while enabling miniaturization of test structures to match chip geometry scaling.
Solution Approach 2:
The test structures are designed to use the same contact structures, interlayer dielectric layers, and manufacturing processes as the main IC chips. This universal approach allows the test structures to be fabricated using existing chip manufacturing capabilities, reducing the need for specialized complex processes while maintaining measurement functionality.
2Productivity
If test structures are made smaller to increase device density, then circuit density improves, but measurement accuracy deteriorates
Solution Approach 1:
The patent applies different quality requirements to different regions: the test structures use the same scaled geometry as the main chips to benefit from high device density, while the contact structures and measurement regions maintain sufficient dimensions for accurate measurement. The interlayer dielectric thickness and contact structure dimensions are optimized locally to ensure measurement accuracy even as overall device size decreases.
3Measurement precision
If complex manufacturing processes are used to improve test structure accuracy, then measurement precision improves, but ease of manufacture deteriorates
Solution Approach 1:
The patent combines test structure manufacturing with main IC fabrication processes, forming test structures, contact structures, and interlayer dielectric layers concurrently with chip structures using the same manufacturing steps. This merging eliminates the need for separate complex processes while maintaining measurement accuracy through proper process integration.
Solution Approach 2:
The test structures utilize the same manufacturing processes and materials as the main IC chips, allowing the existing fabrication infrastructure to serve dual purposes. The chip manufacturing processes automatically create the test structures as well, eliminating the need for separate specialized processes and reducing overall manufacturing complexity.
Data Source
AI summary
A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1.