DRAM Memory Cell Transistor Trench Structure Formation
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Solution Overview
Problem
Existing buried word line processes for DRAM cell transistors face challenges such as contamination and process control difficulties due to the small window for etching bit line contacts, which can damage gate oxides and result in high contact resistance.
Innovation Solution
The method involves forming a trench structure in a substrate, depositing a conductive substance, and then etching dielectric and conductive layers to create a hole structure that extends to the substrate surface, allowing for the formation of bit line contact plugs after polysilicon deposition, thereby reducing contact resistance and avoiding gate oxide contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the small window for etching bit line contacts is used in existing buried word line processes, then the contact resistance is reduced, but the gate oxide is damaged and contamination occurs
Solution Approach 1:
The patent applies preliminary action by forming a protective cap layer over the gate oxide before the etching process. This cap layer is deposited in advance to protect the gate oxide from damage during subsequent etching operations, preventing contamination while allowing precise contact formation.
Solution Approach 2:
The patent uses an intermediary approach by introducing a cap layer as a mediator between the etching process and the gate oxide. This intermediate layer serves as a protective barrier that prevents direct contact between the etching chemicals and the gate oxide, thereby preventing damage while allowing the etching to proceed for contact formation.
2Device complexity
If the buried word line process is used to reduce contact layer, then the device complexity is reduced, but the process control difficulty increases due to small etching window
Solution Approach 1:
The patent applies preliminary action by forming a protective cap layer over the gate oxide before the etching process. This cap layer is deposited in advance to protect the gate oxide from damage during subsequent etching operations, preventing contamination while allowing precise contact formation.
Solution Approach 2:
The patent changes process parameters by introducing a cap layer with specific material properties and thickness that enable better etching control. This parameter change transforms the difficult etching process into a more controllable operation, improving ease of manufacture while maintaining the buried word line structure's simplicity.
3Ease of manufacture
If the etching process is performed to form bit line contacts, then the contact structure is created, but the gate oxide contamination and damage occur
Solution Approach 1:
The patent uses an intermediary approach by introducing a cap layer as a mediator between the etching process and the gate oxide. This intermediate layer serves as a protective barrier that prevents direct contact between the etching chemicals and the gate oxide, thereby preventing damage while allowing the etching to proceed for contact formation.
Solution Approach 2:
The patent applies the taking out principle by removing the harmful effect of etching chemicals from the gate oxide environment. The cap layer extracts or isolates the gate oxide from the damaging etching process, allowing contact formation to proceed without contamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process, enhances bit line contact formation control, and reduces contact resistance, while minimizing damage to gate oxides, resulting in a more reliable and efficient memory cell transistor structure.
Implementation Method 1
depositing a conductive substance on the surface of the substrate wherein the conductive substance at least partially occupies the inner space of the trench structure thereby forming a conductive member inside the trench structure
Implementation Method 2
etching the first conductive layers and the dielectric layers to form a hole structure wherein the hole structure extends through the first conductive layers and the dielectric layers, reaching to the surface of the substrate
Data Source
AI summary
A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure.