DRAM Cell Layout Asymmetry for Zigzag Capacitor Packing
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Solution Overview
Problem
Conventional DRAM memory cell layouts with a 6F2 cell area fail to arrange storage capacitors in a zigzag pattern, limiting their density and capacity, and the use of HSG-Si for MIS capacitors results in inadequate blockage margins and cylinder hole blockage.
Innovation Solution
The layout is optimized by forming active regions at an 18-degree angle to the X direction, with offset storage node contacts and pads, allowing for a high-density, zigzag arrangement of storage capacitors and ensuring adequate HSG blockage margins through precise positioning and alternating pad layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If storage capacitors are arranged in a conventional 6F2 layout, then the cell area is minimized, but the storage capacitors cannot be arranged in zigzag fashion and cannot be packed at maximum density
Solution Approach 1:
The patent applies asymmetry by offsetting the storage node contacts from the cell contacts in the X direction. Specifically, the storage node contacts are positioned at coordinates (4F, 0) while cell contacts are at (2F, 0), creating an asymmetric arrangement that enables zigzag patterning of storage capacitors while maintaining the 6F2 cell area, thereby achieving maximum packing density
2Quantity of substance
If contact plugs are arranged in zigzag fashion, then storage capacitors can be offset for maximum density, but the HSG blockage margin cannot be adequately ensured and cylinder holes become blocked
Solution Approach 1:
The patent resolves the contradiction by introducing dimensional separation: storage node contacts are offset in the X direction (transverse) from cell contacts, while bit line contacts are positioned in the Y direction (longitudinal) at the center portions of active regions. This multi-dimensional arrangement allows zigzag storage capacitor patterning while maintaining adequate spacing for HSG blockage margins
Data Source
AI summary
a semiconductor storage device is provided with a plurality of active regions formed in the shape of a band in a semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction; bit line contacts formed on the first cell contacts; bit lines wired so as to pass over the bit line contacts; storage node contacts formed on the second cell contacts; storage node contact pads formed on the storage node contacts; and storage capacitors formed on the storage node contact pads. The center positions of the storage node contacts are offset in a prescribed direction from the center positions of the second cell contacts. The center positions of the storage node contact pads are offset in a prescribed direction from the center positions of the storage node contacts.