DRAM Cache On-Demand Reload Eliminates Refresh Stalls
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Solution Overview
Problem
Conventional DRAM caches require regular refresh operations, leading to power consumption, read/write stalls, and increased complexity, which hinders their adoption in high-speed caches like level '1' and '2' caches due to refresh cycles and the need for error detection mechanisms.
Innovation Solution
A DRAM cache structure with on-demand reload and error detection schemes, utilizing static and radiation-hardened memory cells as error check bits, eliminates the need for regular refresh, reduces power consumption, and minimizes read/write stalls by detecting and correcting multi-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If regular refresh operations are implemented in DRAM cache, then data retention is maintained, but power consumption increases and read/write stalls occur
Solution Approach 1:
The patent implements periodic refresh operations only when necessary, rather than continuous refreshing. The refresh operation is triggered based on detection of data changes or specific conditions, converting from a continuous periodic action to a conditional periodic action that occurs only when data retention is at risk.
Solution Approach 2:
The DRAM cache employs error detection and correction circuits that automatically detect and correct data retention errors without requiring external intervention or full refresh operations. The system serves itself by monitoring data integrity and performing minimal corrective actions only when needed.
2Reliability
If regular refresh operations are implemented in DRAM cache, then data retention is maintained, but read/write availability decreases
Solution Approach 1:
Instead of continuous periodic refresh that blocks all operations, the patent uses conditional periodic refresh that occurs only when data changes are detected. This allows read/write operations to proceed uninterrupted during normal operation, maintaining high availability while still ensuring data retention when needed.
Solution Approach 2:
The patent extracts the refresh operation from the critical data path by implementing it in a separate background mechanism. Refresh operations are decoupled from read/write operations, allowing them to occur without blocking or stalling the main data access operations, thus maintaining high read/write availability.
3Adaptability or versatility
If DRAM is used instead of SRAM for cache, then low voltage scaling and process variation tolerance improve, but refresh complexity and architecture changes are required
Solution Approach 1:
The patent extracts the refresh functionality from the core DRAM cache architecture by implementing it as a separate, optional background process. This allows the main cache structure to remain simple and SRAM-like, while DRAM-specific refresh requirements are handled by an independent mechanism that can be enabled or disabled based on needs.
Solution Approach 2:
The patent creates a universal cache architecture that can operate in multiple modes: traditional continuous refresh mode, on-demand refresh mode, or even SRAM-like operation. The same basic DRAM cache structure can adapt to different requirements, making it universally applicable across different voltage scaling scenarios and performance requirements.
4Reliability
If error detection mechanisms are added to DRAM cache, then multi-bit error detection capability improves, but device complexity increases
Solution Approach 1:
The patent replaces complex hardware error detection circuits with software-based or logic-based error detection mechanisms. Instead of using additional physical sensors or complex analog circuits to detect errors, the system uses digital logic operations and algorithmic approaches to identify multi-bit errors, significantly reducing hardware complexity.
Solution Approach 2:
The patent introduces an intermediary error detection layer that sits between the DRAM array and the cache control logic. This intermediary mechanism uses simple parity bits or checksums generated by basic logic circuits to detect errors, avoiding the need for complex dedicated error detection hardware while still providing robust multi-bit error detection capability.
Data Source
AI summary
Embodiments include a DRAM cache structure, associated circuits and method of operations suitable for use with high-speed caches. The DRAM caches do not require regular refresh of its data and hence the refresh blank-out period and refresh power are eliminated, thus improving cache availability and reducing power compared to conventional DRAM caches. Compared to existing SRAM caches, the new cache structures can potentially achieve the same (or better) speed, lower power and better tolerance to chip process variations in future process technologies.