DRAM Refresh Scheduling via Idle Rank Monitoring
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Solution Overview
Problem
Conventional DRAM refresh mechanisms often delay access commands due to unnecessary refresh operations, especially in idle ranks, leading to inefficient use of computing resources and potential delays in executing access commands.
Innovation Solution
A DRAM controller with a command queue and microcontroller dynamically schedules refresh operations by repeatedly refreshing idle ranks during an initial refresh inspection interval, allowing access commands to be prioritized and executed without excessive delay, and adjusting priorities based on refresh status to optimize resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM refresh mechanisms are used to ensure data reliability, then data reliability is improved, but access command execution is delayed and computing resources are wasted on unnecessary refresh operations in idle ranks
Solution Approach 1:
The refresh mechanism transitions from a static, periodic refresh schedule to a dynamic, demand-driven refresh approach. The microcontroller monitors rank activity status and dynamically adjusts refresh operations: idle ranks are repeatedly refreshed within the same refresh inspection interval to eliminate future refresh delays, while active ranks have their access commands executed immediately without refresh interference. This dynamic adaptation resolves the contradiction by making refresh operations contingent on actual rank usage patterns.
Solution Approach 2:
The system implements self-service by having the microcontroller autonomously monitor rank activity status and independently adjust refresh schedules without external intervention. The controller detects when ranks are idle and automatically performs repeated refresh operations during the current refresh inspection interval, thereby eliminating the need for future refresh operations on those ranks and reducing access command delays without sacrificing data reliability.
2Reliability
If refresh operations are performed every refresh inspection interval to maintain data reliability, then data reliability is improved, but computing resources are inefficiently utilized and productivity decreases
Solution Approach 1:
The system applies partial refresh action by performing refresh operations selectively based on rank activity status. Instead of uniformly refreshing all ranks every refresh inspection interval, the microcontroller identifies idle ranks and performs repeated refresh operations only on those ranks during the current interval. This partial action approach maintains data reliability for idle ranks while eliminating unnecessary refresh operations on active ranks, thereby improving overall system productivity and resource utilization efficiency.
Solution Approach 2:
The refresh schedule parameter is dynamically changed based on rank activity status. When a rank is detected as idle, the system changes the refresh parameter from periodic (one refresh per interval) to repeated refresh (multiple refreshes within the same interval). This parameter change eliminates future refresh operations for idle ranks, improving productivity without compromising data reliability. The parameter adjustment is made contingent on the actual usage state of each rank.
3Reliability
If per-rank refresh operations are executed regularly to ensure data integrity, then data integrity is improved, but access command priority and execution timing deteriorate
Solution Approach 1:
The system performs preliminary repeated refresh operations on idle ranks during the current refresh inspection interval before access commands need to be executed. By proactively refreshing idle ranks multiple times within the same interval, the system ensures data integrity is maintained while eliminating the need for future refresh operations that would delay access command execution. This preliminary action resolves the contradiction by preparing the system in advance to avoid conflicts between refresh and access operations.
Data Source
AI summary
A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.


