DRAM Refresh Management for Unused Row Address Skipping
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Solution Overview
Problem
Current memory devices, particularly DRAMs, consume high refresh currents due to the need to periodically refresh all memory cell arrays, regardless of usage, leading to inefficiencies as capacity increases.
Innovation Solution
Implementing a refresh management system that skips refresh operations for unused memory areas by mapping virtual addresses to physical addresses and using a refresh skip signal to control the refresh operation, allowing only used memory areas to be refreshed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operation is performed for all memory cell arrays, then data integrity is maintained, but refresh current consumption increases
Solution Approach 1:
The patent applies local quality by differentiating between used and unused memory regions. Instead of uniformly refreshing the entire memory array, the system identifies and refreshes only the locally used portions (first memory region) while skipping unused portions (second memory region). This selective approach maintains data integrity for active data while reducing unnecessary refresh operations in inactive areas, thereby lowering overall refresh current consumption.
Solution Approach 2:
The patent segments the memory array into multiple regions based on usage patterns. The memory is divided into a first memory region that requires refresh operations and a second memory region that does not. This segmentation allows the refresh mechanism to operate independently on different portions of memory, enabling optimized refresh current consumption by focusing resources only on active regions rather than treating the entire memory array uniformly.
2Use of energy by moving object
If refresh operation is skipped for unused memory areas, then refresh current consumption is reduced, but data integrity may be compromised
Solution Approach 1:
The patent implements preliminary action by establishing a usage determination mechanism before executing refresh operations. The system预先 (in advance) identifies which memory regions are actively used and which are unused based on program execution patterns. This preliminary classification allows the refresh mechanism to skip unused regions without compromising data integrity, as only regions with active data access patterns are selected for refreshing, ensuring that skipped regions contain no critical data.
Solution Approach 2:
The patent employs feedback mechanisms through usage determination logic that continuously monitors memory access patterns. The system uses feedback from program execution information to dynamically determine which memory regions require refresh operations. This feedback-driven approach ensures that refresh operations are aligned with actual data usage patterns, maintaining data integrity for active regions while safely skipping unused regions, thus optimizing the balance between energy consumption and reliability.
3Measurement precision
If virtual address mapping is implemented for refresh management, then refresh operation precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a usage determination unit that mediates between the virtual address space and physical memory refresh operations. This intermediary layer translates virtual address information into physical memory region classifications (used vs. unused), enabling precise refresh operations without requiring direct complex address translation circuitry. The usage determination unit acts as a software-friendly mediator that simplifies the overall system architecture while maintaining precise control over which physical memory regions are refreshed.
Data Source
AI summary
A memory device may be provided. The memory device may include an active control section configured to output a row active signal in response to a refresh signal when an active signal is activated. The memory device may include a refresh management section configured to control the refresh signal to skip a refresh operation for an unused row address in response to a refresh command signal and a refresh skip signal, and output an active row address for controlling the refresh operation. The memory device may include a memory section configured to perform a refresh operation for only an area of a cell array corresponding to a used row address in response to the row active signal and the active row address.