DRAM Scheduler Segmentation for Bandwidth and Area Optimization
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Solution Overview
Problem
Conventional DRAM scheduling techniques require complex logic to manage memory access, consuming large die area and increasing power requirements, and are inefficient when handling less than maximum channel configurations.
Innovation Solution
A scalable DRAM scheduling technique using a master scheduler and slave state machines to translate and prioritize DRAM requests, allowing for efficient access to DRAM by managing command streams and reducing the need for tracking maximum channel configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional DRAM scheduling logic is used to manage memory access, then data bandwidth and memory access performance are improved, but die area and power consumption increase
Solution Approach 1:
The scheduling logic is segmented into separate functional units: a request translation unit that converts CPU requests into DRAM commands, and a scheduling unit that manages command sequencing. This segmentation allows each unit to be optimized independently and reduces overall complexity while maintaining high bandwidth performance.
Solution Approach 2:
The patent extracts the channel configuration tracking functionality from the scheduling logic. By separating this tracking function, the system can operate efficiently with fewer than maximum channel configurations without requiring complex scheduling algorithms, thus reducing die area and power consumption while maintaining productivity.
2Productivity
If conventional DRAM scheduling logic is used to manage memory access, then memory access performance is optimized, but power requirements increase
Solution Approach 1:
The power consumption is reduced by segmenting the scheduling logic into efficient functional blocks that operate independently. The request translation and scheduling units work in parallel, reducing the computational burden and energy required for memory access management while maintaining optimized performance.
Solution Approach 2:
The system implements partial scheduling logic that is sufficient for operating with fewer than maximum channel configurations. This partial action approach avoids the excessive computational overhead of full conventional scheduling algorithms, reducing power consumption while maintaining adequate memory access performance for typical workloads.
3Productivity
If conventional DRAM scheduling logic is used, then bandwidth utilization is maximized, but die area increases
Solution Approach 1:
The patent removes the unnecessary channel configuration tracking logic from the die design. By extracting this functionality, the system achieves high bandwidth utilization without requiring the large die area needed for comprehensive scheduling logic, thus resolving the contradiction between productivity and area.
Solution Approach 2:
The scheduling unit is designed with multi-functionality to handle various DRAM command types and configurations through a unified approach. This universal design reduces the need for separate dedicated logic for each function, thereby reducing die area while maintaining high bandwidth utilization across different operating conditions.
Data Source
AI summary
A technique of accessing a resource includes receiving, at a master scheduler, resource access requests. The resource access requests are translated into respective slave state machine work orders that each include one or more respective commands. The respective commands are assigned, for execution, to command streams associated with respective slave state machines. The respective commands are then executed responsive to the respective slave state machines.