DRAM Metadata Storage via Page Section Sequestration

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Solution Overview

Problem

Current computing systems face challenges in efficiently storing metadata with data units in memory systems, as traditional memory chips lack native resources for metadata storage, leading to additional memory chips being added, which increases costs and risks data reliability.

Innovation Solution

A dynamic random access memory (DRAM) design that integrates metadata storage by reserving sections of each page in the memory for metadata, allowing metadata to be transferred as part of a burst transfer process, and utilizing multiplexers to select and transmit the correct metadata bits alongside data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If additional memory chips are added for metadata storage, then metadata storage capacity is improved, but system cost increases

Engineering Contradiction:
Improvemetadata storage capacityVSAvoidsystem cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent combines metadata storage with data storage by allocating a portion of each memory page (e.g., 8 bits out of 64 bits) to store metadata. This merging approach eliminates the need for separate metadata storage chips, thereby maintaining metadata storage capacity while reducing system cost.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory system is designed to serve multiple functions: storing both customer data and metadata within the same memory chips. By making the memory system universal, it eliminates the need for dedicated metadata storage resources, reducing overall system cost while maintaining full metadata storage capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If additional memory chips are added for metadata storage, then metadata storage capacity is improved, but device complexity increases

Engineering Contradiction:
Improvemetadata storage capacityVSAvoidsystem complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

By merging metadata and data storage into a single memory structure, the patent reduces the number of separate components and interconnections required. This simplification directly reduces device complexity while maintaining full metadata storage capacity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If ECC memory chips are used for metadata storage, then data reliability is improved, but system cost increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges metadata storage with the main memory array, allowing metadata to benefit from the same ECC protection already implemented for data storage. This approach maintains data reliability without the additional cost of separate ECC memory chips.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory system provides universal protection, applying ECC error correction to both data and metadata stored within the same chips. This ensures data reliability for all stored information while avoiding the need for specialized ECC memory resources.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If ECC memory chips are used for metadata storage, then data reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By combining metadata storage with the main memory array under a unified ECC protection scheme, the patent reduces the number of separate error correction systems required. This simplification reduces device complexity while maintaining comprehensive data reliability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12210456B2Dynamic random access memory (DRAM) with scalable meta data
Publication Date: 2025.01.28 INTEL CORP
  • US12210456B2 patent drawing
  • US12210456B2 patent drawing
  • US12210456B2 patent drawing

AI summary

A memory is described. The memory includes row buffer circuitry to store a page. The page is divided into sections, wherein, at least one of the sections of the page is to be sequestered for the storage of meta data, and wherein, a first subset of column address bits is to: 1) define a particular section of the page, other than the at least one sequestered sections of the page, whose data is targeted by a burst access; and, 2) define a field within the at least one of the sequestered sections of the page that stores meta data for the particular section.