DRAM Region-Specific Refresh Control for Power Optimization
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face challenges in data retention due to finite capacity, leading to unreliable data over time, which increases power consumption and reduces data input/output bandwidth, and existing solutions complicate DRAM chip production and usage as general-purpose memory by requiring different policies for varying applications.
Innovation Solution
A memory module with a DRAM management unit that includes a memory device operational parameter storage circuit to store refresh operational parameters for dynamic memory devices, allowing for region-specific refresh operations based on master time intervals and dual retention field values, optimizing refresh frequency according to data retention needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently across all DRAM regions, then data retention is improved, but power consumption increases
Solution Approach 1:
The DRAM chip is divided into multiple regions, each with independent refresh control. The memory device operational parameter storage circuit stores separate refresh operational parameters for each region, allowing selective refreshing of only those regions that need it, rather than refreshing the entire chip uniformly.
Solution Approach 2:
Different regions of the DRAM chip are assigned different refresh frequencies based on their specific data retention requirements. Regions with higher data retention needs receive more frequent refresh operations, while regions with lower needs receive less frequent refresh, optimizing the balance between data retention and power consumption.
2Reliability
If refresh operations are performed uniformly across all regions, then data retention is maintained, but data input/output bandwidth is reduced
Solution Approach 1:
The refresh control is segmented by region, allowing independent management of refresh operations for each DRAM region. This enables regions to be refreshed on different schedules, preventing uniform refresh from blocking data I/O operations across the entire chip.
Solution Approach 2:
The refresh operational parameters are dynamically adjusted based on the specific characteristics and usage patterns of each region. The system can adaptively change refresh frequencies and timing for different regions, optimizing the balance between maintaining data retention and preserving data I/O bandwidth.
3Use of energy by moving object
If region-specific refresh policies are implemented, then power consumption is optimized, but device complexity increases
Solution Approach 1:
The DRAM chip includes built-in operational parameter storage circuits and control logic that automatically manage region-specific refresh operations. The system self-regulates the refresh timing and frequency for each region based on stored parameters, eliminating the need for external controller intervention and reducing overall system complexity.
Solution Approach 2:
The memory device operational parameter storage circuit serves multiple functions: it stores refresh operational parameters, tracks refresh timing for each region, and provides control signals for selective refresh operations. This multi-functionality reduces the need for separate dedicated circuits for each refresh control task.
4Reliability
If different refresh policies are required for varying applications, then data retention is optimized, but ease of manufacture is reduced
Solution Approach 1:
The DRAM chip is manufactured with segmented regions that can be independently configured for different applications. Each region has its own operational parameter storage circuit that can be programmed with appropriate refresh policies during or after manufacturing, allowing a single chip design to serve multiple application needs without requiring different manufacturing processes.
Data Source
AI summary
A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.