DRAM Refresh Unit Voltage Compensation for Degraded Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic random access memory (DRAM) systems face challenges in maintaining data integrity due to capacitor degradation over time, leading to incorrect binary logic interpretation and increased power consumption from frequent refresh operations.
Innovation Solution
A DRAM system with a refresh unit comprising a first cell for storing data and a second cell for monitoring degradation, where the control device adjusts the voltage difference between the programmed voltage level and the standard voltage level by decreasing the standard voltage level or increasing the program voltage when the test voltage level falls below a threshold, allowing for reduced refresh rates and efficient power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh rate is increased to maintain data integrity in degraded capacitors, then data correctness is improved, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameter dynamically based on capacitor degradation state. When degradation is detected through the test cell, the system adjusts the read voltage level to compensate for the degraded capacitor's inability to maintain voltage, thereby maintaining data correctness without increasing refresh rate
Solution Approach 2:
The patent implements a feedback mechanism where the test cell monitors the state of data cells, and this information feeds back to the control device which adjusts the read voltage accordingly. This closed-loop system allows the DRAM to adapt to degradation and maintain reliability without excessive refreshing
2Measurement precision
If the voltage difference between programmed voltage level and standard voltage level is increased to ensure correct binary logic interpretation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the control device multi-functional by having it perform both normal read operations and degradation compensation functions. The same control device that manages standard read/write operations also dynamically adjusts voltage levels based on degradation feedback, eliminating the need for separate complexity-added circuits
3Reliability
If test cells are added to monitor capacitor degradation, then reliability monitoring is improved, but device complexity increases
Solution Approach 1:
The patent uses a simplified copy approach where test cells replicate the essential degradation-prone capacitor structure but are dedicated solely to monitoring purposes. This allows degradation detection without the full complexity of functional memory cells, providing reliability monitoring with minimal added complexity
Data Source
AI summary
A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.