DRAM Refresh Control Path with Multiple Activations
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Solution Overview
Problem
As memory components decrease in size, the increased density of memory cells in semiconductor devices like DRAM requires more frequent refresh operations to maintain data integrity, necessitating efficient and flexible methods for refreshing memory cells.
Innovation Solution
The semiconductor device employs a refresh control path with multiple refresh activations within a refresh cycle, including a double-pump per bank and all-bank refresh operation, utilizing trimmable delays to optimize timing and reduce peak power consumption, allowing for 'hidden' refresh operations to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory components decrease in size to increase density, then memory cell density increases, but the number of refresh operations required increases
Solution Approach 1:
The memory array is divided into multiple banks, and each bank is further divided into sub-arrays that can be refreshed independently. This segmentation allows the refresh operations to be distributed across different banks and time periods, reducing the overall refresh burden on any single bank while maintaining high memory cell density.
Solution Approach 2:
The patent implements periodic refresh operations where different banks are refreshed in alternating cycles. By staggering the refresh timing across multiple banks, the system can maintain high density memory cells while distributing the refresh operations over time, preventing any single refresh cycle from becoming overwhelming.
2Ease of operation
If traditional single refresh activation per cycle is used, then refresh operation simplicity is maintained, but peak power consumption increases
Solution Approach 1:
The refresh operation is segmented into multiple activations within a single refresh cycle. Instead of one large simultaneous refresh, the system performs multiple smaller refresh operations on different banks sequentially. This segmentation reduces the peak current draw while maintaining comprehensive refresh coverage, thus lowering peak power consumption.
Solution Approach 2:
Multiple refresh activations are distributed periodically throughout the refresh cycle rather than occurring simultaneously. This periodic distribution of refresh operations smooths out power consumption peaks while ensuring all memory banks receive their required refresh operations, effectively reducing peak power consumption.
3Use of energy by stationary object
If multiple refresh activations are implemented within a refresh cycle, then peak power consumption is reduced, but control path complexity increases
Solution Approach 1:
The control path is segmented into separate control logic for different banks, with each bank having its own refresh control mechanisms. This modular segmentation allows multiple refresh activations to be managed independently in different banks, reducing the complexity burden on any single control unit while enabling coordinated multi-activation operation.
Solution Approach 2:
The control path uses periodic enable signals and timing mechanisms to orchestrate multiple refresh activations. By using regular periodic patterns for activating different banks, the control logic remains relatively simple and predictable, avoiding the need for complex arbitrary scheduling while still achieving reduced peak power consumption through distributed refresh operations.
Data Source
AI summary
A system for refresh operations including multiple refresh activations, and a method and an apparatus therefore, are described. The system includes, for example, a memory array; a command address input circuit configured to provide a command for a per bank refresh operation or an all-bank refresh operation, a command control circuit configured to receive the command, and provide first and second internal control signals; a refresh control circuit configured to provide a first refresh control signal; and a row control circuit configured to provide a second refresh control signal. The provided first internal control signal is based on the provided command. For the per bank refresh operation, the provided second internal control signal is based on the second refresh control signal, and, for the all-bank refresh operation, the provided second internal control signal is based on the first internal control signal delayed by the command control circuit.