DRAM ReRAM MIM Structure Depth Optimization
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing manufacturing costs while maintaining performance when integrating DRAM and ReRAM on a single chip, as existing methods either fail to sufficiently lower costs or compromise performance due to parasitic capacitance and material inefficiencies.
Innovation Solution
The integration of a semiconductor memory device with a variable resistance element having a cylinder-type MIM structure and a capacitance element with a deeper cylinder-type MIM structure, allowing for shared manufacturing processes and reduced parasitic capacitance, thereby reducing manufacturing costs and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same MIM structure is used for both DRAM capacitance element and ReRAM variable resistance element, then manufacturing cost is reduced through shared processes, but performance of both elements cannot be sufficiently optimized
Solution Approach 1:
The patent applies local quality by differentiating the MIM structure characteristics for DRAM and ReRAM elements. Specifically, the capacitance element MIM structure has different electrode material composition, insulating film thickness, and geometric dimensions compared to the variable resistance element MIM structure. This allows each element type to have optimized local properties for its specific function while still using a shared manufacturing process framework
Solution Approach 2:
The patent utilizes parameter changes by adjusting key MIM structure parameters including electrode material composition ratios, insulating film thickness, and overall MIM structure dimensions. These parameter variations enable the same manufacturing process to produce both DRAM capacitance elements and ReRAM variable resistance elements with their respective optimal performance characteristics
2Reliability
If the MIM area is increased to improve DRAM capacitance element performance, then DRAM capacity increases, but parasitic capacitance of the MIM structure increases which degrades ReRAM performance
Solution Approach 1:
The patent applies segmentation by spatially separating the DRAM capacitance element MIM structure from the ReRAM variable resistance element MIM structure on the substrate. This physical segmentation allows the DRAM MIM to have larger area for higher capacitance without the parasitic capacitance directly affecting ReRAM operation, as the harmful effect is isolated to the DRAM region
Solution Approach 2:
The patent uses an intermediary approach by introducing separate transistor structures and wiring configurations that mediate between the DRAM and ReRAM elements. The DRAM-specific transistors and bit lines act as intermediaries that allow the DRAM MIM to be optimized for capacitance without directly exposing the ReRAM element to the parasitic capacitance effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of manufacturing costs while maintaining the performance of both capacitance and variable resistance elements, achieving faster operational speeds and lower power consumption by optimizing the depth and structure of the MIM elements.
Implementation Method 1
The variable resistance element (1) of the variable resistance type memory has a cylinder type MIM (Metal-Insulator-Metal) structure with a first depth (D1)
Implementation Method 2
The capacitance element (101) of the DRAM (Dynamic Random Access Memory) has a cylinder type MIM structure with a second depth (D2)
Implementation Method 3
in the ReRAM, since a parasitic capacitance of the MIM prevents the improvement in performance of the ReRAM, it is necessary to reduce its capacity
Data Source
AI summary
In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.