DRAM Data Sensing Asymmetry and Charge Sharing
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Solution Overview
Problem
Conventional data sensing methods for DRAM suffer from decreased sensing margin due to voltage variation caused by coupling noise, offset noise, and capacitor leakage, especially under low supply voltage, leading to increased error percentages.
Innovation Solution
The proposed data sensing method involves keeping the transistor in the off state when the stored data is a predetermined value and turning it on when the data is opposite, allowing a charge sharing process between the storage capacitor and parasitic capacitor, while adjusting voltages to enhance the sensing margin by ensuring the sense amplifier can accurately differentiate between the two states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional data sensing method divides sensing margin equally between two states, then the sensing method is simple to implement, but the sensing margin decreases due to voltage variation from coupling noise, offset noise, and capacitor leakage
Solution Approach 1:
The patent applies asymmetry by allocating sensing margin unequally between the two data states. Specifically, when stored data is '0', the bit line voltage is allowed to vary within a larger range (from Vcc/2 - Vm to Vcc/2 + Vm), while when stored data is '1', the voltage variation range is smaller (from Vcc/2 to Vcc/2 + Vm). This asymmetric voltage allocation ensures that the sense amplifier can reliably distinguish between states despite noise and leakage, thereby improving sensing margin without requiring complex additional circuitry.
Solution Approach 2:
The patent employs preliminary action by pre-charging the bit line to a specific voltage (Vcc/2) before the sensing operation begins. This pre-charging step prepares the bit line in advance to be in a known state, allowing the sense amplifier to accurately detect subsequent voltage changes caused by charge sharing between the storage capacitor and bit line parasitic capacitance. This preliminary preparation reduces the impact of noise and leakage on the sensing margin.
2Use of energy by moving object
If supply voltage Vcc is reduced to achieve low power consumption, then power consumption decreases, but the sensing margin continues to decrease and error percentage increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage levels and sensing thresholds based on the stored data state. When data is '0', the system allows the bit line voltage to swing to Vcc/2 - Vm, and when data is '1', it swings to Vcc/2 + Vm. This parameter adjustment optimizes the voltage difference detected by the sense amplifier, maintaining adequate sensing margin even when the supply voltage Vcc is reduced for low power consumption.
3Measurement precision
If the transistor is always turned on for sensing, then the sensing process is straightforward, but the voltage difference on the bit line becomes too small to be reliably sensed under low supply voltage
Solution Approach 1:
The patent applies dynamics by conditionally controlling the transistor state based on the stored data. The transistor is turned on only when the stored data is '0' to enable charge sharing between the storage capacitor and bit line parasitic capacitance, creating a detectable voltage difference. When the stored data is '1', the transistor remains off, and the sense amplifier detects the pre-charged bit line voltage directly. This dynamic control ensures sufficient voltage difference for reliable sensing while maintaining operational simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the sensing margin, making it applicable to DRAMs under low supply voltage and reducing error percentages by allocating sensing margin completely to one state, thereby improving data accuracy.
Implementation Method 1
a storage capacitor (30) configured to store data
Implementation Method 2
a transistor (20) connecting the storage capacitor and the bit line... turning on the transistor when the stored data is opposite to the predetermined value such that a charge sharing process occurs
Implementation Method 3
enabling the sense amplifier to sense the voltage of the bit line and the reference bit line
Data Source
AI summary
A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the reference bit line. The data sensing method comprises the steps of turning off the transistor when the stored data is a predetermined value before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line, and turning on the transistor when the stored data is opposite to the predetermined value such that a charge sharing process occurs between the storage capacitor and a parasitic capacitor of the bit line before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line.