DRC Code Conflict Detection via Segmentation and Classification
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Solution Overview
Problem
In chip design, the lack of clear distinctions in design rules leads to numerous errors during the design rule check (DRC) process, prolonging development time and reducing efficiency due to the need for manual examination of millions of potential errors in the DRC code file.
Innovation Solution
A design rule check method and apparatus that analyzes DRC code segments, classifies them, and generates reports for code conflicts and redundancies, allowing designers to correct the DRC code or Design Rule Manual (DRM) before generating a test pattern, thereby reducing errors and improving execution efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual examination of DRC code segments is performed to identify errors, then measurement precision of code conflicts is improved, but loss of time increases due to examining millions of errors one by one
Solution Approach 1:
The patent segments the DRC code file into multiple DRC code segments and processes them in parallel using multiple processing threads. This segmentation allows the system to divide the overwhelming task of examining millions of errors into manageable chunks, maintaining measurement precision while dramatically reducing the time required by enabling concurrent processing across multiple threads.
Solution Approach 2:
The patent performs preliminary classification and conflict detection on DRC code segments before full verification. By pre-processing the code segments to identify potential conflicts and organize them by type, the system prepares the data structure in advance, which accelerates the subsequent error examination process and reduces the time needed to analyze millions of errors while maintaining accurate detection.
2Reliability
If comprehensive DRC code analysis is performed to identify all code conflicts, then reliability of design rule checking is improved, but device complexity increases due to multiple processing threads and classification mechanisms
Solution Approach 1:
The patent divides the DRC code file into multiple segments and processes each segment independently through separate processing threads. This segmentation maintains reliability by ensuring thorough analysis of all code segments while managing complexity through modular, independent processing units that can be scaled systematically rather than requiring a monolithic complex system.
Solution Approach 2:
The patent changes the processing parameters by introducing thread numbers and classification categories as controllable variables. This allows the system to adapt its complexity level based on the specific DRC code characteristics, maintaining high reliability through comprehensive analysis while managing overall system complexity through parameter-based control rather than fixed complex architecture.
3Productivity
If parallel processing with multiple threads is implemented to reduce DRC development time, then productivity is improved, but device complexity increases due to thread management overhead
Solution Approach 1:
The patent segments the DRC code file into multiple processable units and assigns them to different processing threads. This segmentation enables parallel processing that improves productivity by utilizing multiple cores simultaneously, while the modular nature of segmented processing simplifies thread management compared to attempting to process the entire code base in parallel monolithically.
Solution Approach 2:
The patent introduces a classification mechanism as an intermediary that organizes DRC code segments before parallel processing. This intermediary structure simplifies thread management by pre-organizing the work distribution, allowing threads to process pre-classified segments without complex coordination overhead, thus improving productivity while controlling the complexity of parallel processing.
Data Source
AI summary
The present application provides a design rule check method and apparatus, and a storage medium, which are applied to the field of chip verification. The method includes that: a DRC code file is acquired, multiple segments of DRC codes in the DRC code file are analyzed, the analyzed segments of DRC codes are classified, whether a code conflict exists in the segments of DRC codes is determined, and if the code conflict exists, a code conflict report is generated, the code conflict report being used to indicate a code position of the code conflict. By means of the method, the code error in the DRC code file can be quickly checked and positioned, assisting a tester in modifying a DRM file and the DRC file, so as to improve the execution efficiency of the DRC code, and meanwhile, shorten the time for DRC development.


