Design Rule Check Heatmaps Before Routing with J-Net Plus
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing machine learning approaches for predicting Design Rule Violations (DRVs) in integrated circuits face challenges such as imbalanced data and randomness in DRV distribution due to parallel detailed routing, leading to inefficient and noisy predictions, especially in sub-10 nanometer IC chip designs.
Innovation Solution
The use of a customized convolutional neural network architecture, J-Net Plus, which incorporates a focal likelihood loss function and Gaussian random field layer to address the randomness and imbalanced data issues, enabling accurate DRC hotspot and heatmap predictions by considering high-resolution pin shapes and low-resolution layout information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing machine learning approaches are used for predicting Design Rule Violations, then prediction capability is provided, but prediction accuracy deteriorates due to imbalanced data and randomness in DRV distribution
Solution Approach 1:
The patent applies preliminary action by performing physical synthesis and generating DRC density maps before the routing operation to predict DRV locations in advance. This allows the system to identify potential violation areas beforehand, enabling preventive design adjustments before actual routing occurs, thus improving prediction accuracy and reliability
Solution Approach 2:
The patent introduces an intermediary machine learning model that processes DRC density maps as intermediate representations between the placement design and final routing. This intermediary model transforms complex routing randomness into predictable density patterns, allowing accurate DRV prediction without directly observing the stochastic routing process
2Measurement precision
If high-resolution pin shapes and low-resolution layout information are considered in predictions, then prediction accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies dimensionality change by processing pin shapes at high resolution while maintaining layout information at low resolution, combining multiple dimensional representations in the DRC density map. This multi-scale approach captures critical geometric details where needed while avoiding unnecessary computational complexity in less critical areas, achieving accurate hotspot prediction with manageable model complexity
Data Source
AI summary
Design rule violations (“DRVs”) may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.