Automated DRC Rule Deck Verification Engine for IC Layouts
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Solution Overview
Problem
Manual Design Rule Check (DRC) in integrated circuit layout leads to late detection of physical verification errors, causing significant economic losses due to incomplete compliance with design rules, resulting in failed chip production.
Innovation Solution
A check tool and method incorporating an intelligent database creation engine, arrangement engine, and detection and analysis engine to generate test case databases, standard integrated circuit layouts, and analyze target DRC rule decks, ensuring consistency with Design Rule Manual (DRM) specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual DRC is performed by layout engineer, then flexibility and adaptability are maintained, but detection precision and reliability are insufficient leading to late error discovery
Solution Approach 1:
The patent replaces the manual mechanical verification process with an automated intelligent detection system. The intelligent detection and analysis engine automatically verifies design rules without human intervention, substituting the manual mechanical approach with an automated intelligent system that achieves both high precision and full automation.
Solution Approach 2:
The patent introduces an intermediary intelligent detection system that acts as a mediator between the layout design and final verification. This intermediary engine performs automated detection and analysis, bridging the gap between manual design creation and final quality assurance, thereby improving both precision and automation level.
2Productivity
If manual DRC is performed, then device complexity is low, but productivity and manufacturing yield are reduced due to late error detection
Solution Approach 1:
The patent applies preliminary action by performing automated design rule verification early in the design process rather than late in manufacturing. The intelligent detection engine checks for errors before chip production, preventing defects from reaching the manufacturing stage and thereby improving productivity and manufacturing yield despite the increased system complexity.
Solution Approach 2:
The patent replaces simple manual verification with an automated intelligent system that, while more complex, dramatically improves productivity by preventing errors early. The automated engine processes designs faster and more reliably than manual methods, achieving high productivity gains that justify the increased device complexity.
3Loss of time
If manual verification is used, then ease of operation is maintained, but loss of time occurs due to late stage error discovery
Solution Approach 1:
The patent performs verification actions preliminarily and automatically, detecting errors at the design stage rather than at manufacturing. This preliminary automated detection eliminates time loss by catching issues early, while the automation handles the operational complexity, maintaining ease of use for the overall process.
Solution Approach 2:
The intelligent detection engine performs self-service verification automatically without requiring manual operation. The system serves itself by autonomously detecting and analyzing design rules, eliminating time loss from manual verification while maintaining operational simplicity through full automation.
Data Source
AI summary
Embodiments of the application disclose a check tool and a check method for a Design Rule Check (DRC) rule deck of an integrated circuit layout. The check tool (100) for the DRC rule deck of the integrated circuit layout includes: an intelligent database creation engine (110), configured to generate a test case database; an intelligent arrangement engine (120), configured to generate a standard integrated circuit layout (150) according to the test case database; and an intelligent detection and analysis engine (130), configured to detect and analyze a target DRC rule deck (140) of the integrated circuit layout according to the standard integrated circuit layout (150).


