Design Rule Check Verification Using Synthetic Test Cases
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Solution Overview
Problem
The high costs and complexity of semiconductor device fabrication necessitate effective design rule checks (DRCs) to ensure compliance with design rules, as minor errors can lead to significant increases in fabrication costs due to the expensive masks required for advanced technology processes.
Innovation Solution
A method is described for verifying design rule checks by creating a DRC deck based on a design rule manual, generating physical layout test cases using primitive and collection objects, organizing them into a combined database, running the DRC deck, identifying and correcting unintentional failures, and verifying the compliance of the design rule checks to ensure a functional semiconductor device is produced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design rule checks are performed using traditional methods, then fabrication costs can be controlled, but the complexity and time required for verification increase
Solution Approach 1:
The patent creates synthetic test cases that replicate physical layout scenarios to verify DRC rules. These test cases are simplified representations (copies) of actual semiconductor layouts that can be systematically generated and analyzed to ensure design rule compliance without requiring analysis of every possible complex layout scenario.
Solution Approach 2:
The verification process is divided into multiple test cases, each targeting specific design rules or layout scenarios. The synthetic test cases are segmented into distinct categories (e.g., minimum spacing, minimum width, enclosure rules) allowing systematic verification of individual rules independently, reducing overall verification complexity.
2Reliability
If comprehensive design rule checks are performed, then fabrication errors are reduced, but the time required for verification increases
Solution Approach 1:
The patent pre-generates a comprehensive set of synthetic test cases before actual DRC verification is needed. These test cases are prepared in advance and organized in a database, allowing rapid verification without requiring time-consuming on-demand generation of test scenarios during the actual design review process.
Solution Approach 2:
By creating synthetic copies of potential layout scenarios, the system can quickly verify multiple design rules simultaneously without re-analyzing complex real layouts for each rule. The synthetic test cases serve as pre-prepared templates that accelerate the verification process while maintaining comprehensive coverage.
3Measurement precision
If design rule check decks are created from scratch, then verification accuracy is improved, but the time and resources required increase
Solution Approach 1:
The patent creates a universal database of synthetic test cases that can be used to verify multiple different design rules and technology nodes. The same framework and test case generation methodology can be applied across different semiconductor processes, eliminating the need to create verification decks from scratch for each new technology node.
Solution Approach 2:
The verification deck framework and test case library are built in advance using predetermined synthetic scenarios. This preliminary creation of the verification infrastructure allows rapid deployment and updates for new design rules without requiring time-consuming reconstruction of the entire verification system.
Data Source
AI summary
A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.