Automated Test Layout Generation for DRC Deck Verification
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Solution Overview
Problem
The manual generation of test layouts for Design Rule Checking (DRC) decks is limited by the imagination, expertise, and diligence of the person creating them, and existing automated methods may not adequately cover the rules of a specific DRC deck, leading to incomplete or excessive test layouts.
Innovation Solution
A computer-implemented method for automated generation of test layouts that applies random changes to polygon parameters, optimizing layouts to minimize slack with respect to design rule constraints, focusing on topology and distance randomization to efficiently sample interesting cases, thereby generating a comprehensive set of test layouts that effectively verify DRC decks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If manual generation of test layouts is used, then the quality and relevance of test layouts can be controlled, but the quantity and coverage of test layouts are limited by human imagination and expertise
Solution Approach 1:
The patent applies parameter changes by systematically varying polygon parameters (coordinates, dimensions, shapes) to generate diverse test layouts. The method modifies parameters such as polygon vertex positions, edge lengths, and geometric properties to create layouts that cover different design rule scenarios, enabling automated generation of comprehensive test cases without human intervention
Solution Approach 2:
The system performs self-service by automatically generating test layouts without requiring human expertise or imagination. The automated tool independently creates test cases, selects polygons, determines test scenarios, and generates layouts that verify DRC deck rules, freeing users from manual creation limitations
2Productivity
If automated generation of test layouts is used, then the quantity of test layouts can be increased, but the coverage and relevance to specific DRC rules may be insufficient
Solution Approach 1:
The patent implements feedback mechanisms where the generated test layouts are evaluated against the DRC deck rules, and the results feed back into the generation process. The system analyzes which design rules are covered and which are not, adjusting the parameter variation strategies to ensure comprehensive coverage of all DRC rules in the deck
Solution Approach 2:
The method applies preliminary action by pre-defining the DRC deck rules and using them to guide the test layout generation process. The system预先 determines which polygons and parameters need to be varied based on the DRC rules, ensuring that generated layouts are relevant and comprehensive before actual verification occurs
3Reliability
If exhaustive generation of test layouts is attempted, then complete coverage of design rules is achieved, but the number of layouts grows exponentially
Solution Approach 1:
The patent applies segmentation by dividing the test layout generation into manageable components. Instead of generating all possible layouts at once, the system segments the parameter space into discrete categories (e.g., different polygon types, edge configurations, spacing scenarios) and generates test layouts for each segment systematically, reducing overall complexity while maintaining comprehensive coverage
Solution Approach 2:
The method uses partial action by generating only the necessary test layouts that are relevant to the DRC rules. Rather than exhaustively generating all possible layouts, the system identifies and creates only those layouts that test specific design rule constraints, avoiding unnecessary generation of redundant or irrelevant test cases
Data Source
AI summary
A computer-implemented method for automated generation of test layouts for verifying a DRC deck. The method comprises receiving a first layout (L1) comprising one or more polygon shapes (P1) defined by a plurality of polygon parameters (W1,H1). Design rules (R1,R2) are received comprising inequality constraints (C) on the polygon parameters (W1,H1). A second layout (L2) is calculated by applying a random change (ΔW12) of value to at least one of the polygon parameters (W1) of the first layout (L1). A third layout (L3) is calculated by varying values of the polygon parameters (W1,H1) of the second layout (L2) until a respective slack (S1,S2) of the polygon parameters (W1,H1) with respect to one or more of the parameter boundaries (B1,B2) defined by the constraints is minimized. The third layout (L3) may be stored as candidate test layout.