DRC Tool for Early-Stage IC Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRC tools take excessively long to process early-stage 'dirty' IC layout designs, generating overwhelming amounts of rule violations and requiring significant computer resources, making it impractical for timely error identification and correction.
Innovation Solution
An improved DRC tool that automatically recognizes and eliminates problematic cell placements, optimizes the order of rule checks, and limits processing time or errors, providing error reports in both textual and graphical formats to facilitate faster and more manageable data interpretation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRC tools process early-stage 'dirty' IC layout designs, then complete rule checking is performed, but processing time becomes excessively long and computer resources are significantly consumed
Solution Approach 1:
The patent segments the DRC processing into multiple passes: a first pass that performs complete rule checking on all cells, and subsequent passes that focus only on newly added or modified cells. This segmentation allows the system to maintain reliability for complete checking when needed while significantly reducing processing time for incremental updates.
Solution Approach 2:
The patent performs preliminary identification and removal of unchanged cells before conducting DRC rule checks. By预先 removing cells that have not changed from the previous version, the system avoids redundant checking and significantly reduces processing time while maintaining complete coverage of all relevant rules on the modified portions.
2Reliability
If conventional DRC tools check all cells in dirty layout designs, then comprehensive error detection is achieved, but overwhelming amounts of rule violations are generated
Solution Approach 1:
The patent extracts and removes unchanged cells from the DRC processing scope before rule checking. By taking out these cells that are known to be unchanged and will not generate new violations, the system avoids generating overwhelming amounts of redundant rule violation data while maintaining complete error detection on all relevant modified portions.
3Reliability
If conventional DRC tools process all cells regardless of changes, then thorough verification is achieved, but computer resources are significantly consumed
Solution Approach 1:
The patent performs preliminary identification of unchanged cells and removes them from the processing scope before DRC rule checking. This preliminary action prevents redundant computation on cells that have not changed, significantly reducing computer resource consumption (CPU, memory, disk I/O) while maintaining thorough verification on all modified portions through complete rule checking.
4Reliability
If complete DRC rule checking is performed on dirty layouts, then all rule violations are identified, but error reporting becomes unmanageable
Solution Approach 1:
The patent extracts unchanged cells from the processing scope, which prevents the generation of redundant rule violation reports for cells that have not changed. This results in more manageable error reports that contain only the new or modified violations, making it easier for users to interpret and correct errors while maintaining complete identification of all relevant rule violations.
Data Source
AI summary
A DRC tool optimized for analyzing early-stage (“dirty”) IC layout designs by performing one or more of (a) automatically selectively focusing DRC processing to selected regions (i.e., layers and/or cells) of a dirty IC layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during DRC processing to provide the user with a manageable amount of error data in a predetermined reasonable amount of time, and (c) automatically providing error data in a graphical manner using a contrasting dot to indicate the location of each rule violation, whereby relevant problem areas of the dirty IC layout design are easily identified for correction by a human user, and non-relevant areas (e.g., missing block regions) can be efficiently identified and ignored, thereby facilitating efficient modification of the IC layout design.