DRC Violation Prediction for Placement Layouts

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Solution Overview

Problem

Existing electronic circuit design processes face challenges in predicting and preventing design rule check (DRC) violations due to routing congestion, which hinders the minimization of chip size and increases design implementation time.

Innovation Solution

A DRC violation prediction system utilizing machine learning techniques to analyze placement layouts before routing, identifying regions prone to DRC violations and adjusting the layout to avoid them, thereby reducing congestion and optimizing routability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If routing is performed on a placement layout, then circuit interconnections are established, but routing congestion occurs causing DRC violations

Engineering Contradiction:

ImproveDRC complianceVSAvoidrouting congestion

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary analysis of the placement layout before routing to predict potential DRC violations and routing congestion. By identifying problematic regions in advance, the system can alert designers to adjust the placement layout proactively, preventing routing congestion before it occurs and ensuring DRC compliance in the final routed design.

Inventive Principle:

Principle #10Preliminary action

2Area of stationary object

If chip size is minimized, then area efficiency improves, but routing congestion increases leading to DRC violations

Engineering Contradiction:

Improvechip areaVSAvoidDRC compliance

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The system analyzes the placement layout before routing to predict DRC violations that would occur at minimized chip sizes. This preliminary detection allows designers to evaluate whether a compact layout will meet DRC requirements, enabling informed decisions about chip size optimization while maintaining compliance.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system provides feedback to designers about predicted DRC violations in compact layouts. This feedback mechanism allows designers to iteratively adjust the placement layout to achieve better area efficiency while maintaining DRC compliance, as the system continuously evaluates and reports potential issues.

Inventive Principle:

Principle #23Feedback

3Area of stationary object

If placement layout is optimized for area, then chip size reduces, but design implementation time increases due to DRC violations

Engineering Contradiction:

Improvechip areaVSAvoiddesign implementation time

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The system performs preliminary DRC violation prediction on optimized placement layouts before routing is executed. By identifying potential issues in advance, the system prevents time-consuming iterative routing and DRC checking cycles, thereby reducing overall design implementation time while maintaining area optimization.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system provides rapid feedback on predicted DRC violations in optimized layouts, enabling designers to quickly assess whether area optimization will lead to compliance issues. This fast evaluation loop reduces the time required for design iteration and implementation.

Inventive Principle:

Principle #23Feedback

4Reliability

If routing congestion is reduced by increasing spacing, then DRC violations decrease, but chip area increases

Engineering Contradiction:

ImproveDRC complianceVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The system predicts DRC violations in the placement layout before routing, allowing designers to evaluate whether spacing increases are actually needed. By providing advance warning of potential violations, the system enables targeted spacing adjustments only in critical regions rather than blanket increases, minimizing area impact while ensuring compliance.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11816417B2Rule check violation prediction systems and methods

Publication Date: 2023.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.