DRCLock Bit Gating for Forward Link MAC Channel Capacity
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Solution Overview
Problem
The forward link MAC channel in CDMA2000 EVDO RevA/RevB wireless communications is overloaded due to simultaneous transmissions, leading to a high error rate of ACK/NAK and PCB bits, causing delays and reducing throughput, with the DRCLock bits being a significant contributor to this loading and limiting reverse link traffic capacity.
Innovation Solution
The DRCLock bits are selectively gated-off or eliminated during sub-packet durations when ACKs are transmitted, with the Access Terminal assuming a good DRC channel based on ACKs and determining channel quality from ACK/NAK statistics when data traffic is present, and using DRC data quality indications when no data traffic is present, thereby reducing MAC channel loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRCLock bits are transmitted continuously on the FL MAC channel, then the AT can accurately determine DRC channel quality, but the FL MAC channel becomes overloaded leading to high error rates and reduced throughput
Solution Approach 1:
The patent applies periodic action by making DRCLock bit transmission conditional rather than continuous. The AN transmits DRCLock bits only during specific periods when NAK is sent to the AT, and gates off transmission during ACK periods. This periodic/conditional transmission pattern reduces overall channel loading while maintaining necessary channel quality feedback functionality.
Solution Approach 2:
The patent extracts the DRCLock bit transmission from the continuous stream and removes it during ACK periods. By taking out the unnecessary DRCLock transmissions during ACK sub-packets and keeping them only during NAK sub-packets, the solution reduces MAC channel loading while preserving essential channel quality information feedback.
2Loss of information
If the AN transmits DRCLock bits during every sub-packet duration, then the AT has continuous channel quality information, but the MAC channel loading increases causing delays and error rates
Solution Approach 1:
The patent implements periodic action by transmitting DRCLock bits only during NAK sub-packets and gating them off during ACK sub-packets. This conditional periodic transmission reduces the frequency of DRCLock bit transmissions, thereby reducing MAC channel loading and associated delays while still providing channel quality information when needed (during NAK conditions).
Solution Approach 2:
The patent applies self-service by enabling the AT to infer DRC channel quality from the presence or absence of DRCLock bits and from ACK/NAK statistics. The AT can determine channel quality conditions by analyzing whether DRCLock bits are transmitted and by evaluating ACK/NAK patterns, reducing the need for continuous explicit DRCLock bit transmissions.
3Measurement precision
If DRCLock bits are always transmitted to indicate DRC channel quality, then the AT can make accurate rate adaptation decisions, but the FL MAC channel capacity is consumed limiting RL traffic capacity
Solution Approach 1:
The patent extracts DRCLock bit transmission from the continuous stream and removes it during ACK periods where it is redundant. By taking out unnecessary DRCLock transmissions during ACK sub-packets and retaining them only during NAK sub-packets, the solution frees up MAC channel capacity for RL traffic while maintaining necessary channel quality feedback functionality.
Solution Approach 2:
The patent applies multi-functionality by using the ACK/NAK mechanism to serve dual purposes: not only for error control but also for implicit channel quality indication. The presence or absence of DRCLock bits combined with ACK/NAK patterns provides channel quality information, allowing the system to eliminate dedicated DRCLock transmissions during ACK periods while still maintaining measurement precision through alternative means.
Data Source
AI summary
In an H-ARQ system, when the AN is receiving packet data traffic on the RL from an AT and is generating ACKs and NAKs according to the ability of the AN to properly decode such data, the AN gates-off a DRCLock bit within in a sub-packet duration in which an ACK is transmitted on the FL MAC channel. When it receives an ACK, the AT ignores the non-transmitted DRCLock bit in a current sub-packet duration, and assumes that the DRC channel is “good”. When the AN sends a NAK to the AT, it also sends the DRCLock bit. When the AT receives a NAK in a sub-packet duration, it reads and processes whatever DRCLock bit is received during that sub-packet duration. When no data traffic is transmitted on the RL traffic channel, corresponding DRCLock bits are not gated-off by the AN and are transmitted to the AT. The AT then processes the received DRCLock bits. In an alternative embodiment, transmission of DRCLock is totally eliminated.