Drift-Layer Trap Engineering for Stable On-Voltage and Switching Loss
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Solution Overview
Problem
Existing power semiconductor devices face challenges in achieving consistent trade-off characteristics between on voltage and switching loss across different silicon-based semiconductor materials.
Innovation Solution
A semiconductor device is designed with a specific structure, including a semiconductor substrate, a drift layer, an impurity diffusion layer, and a buffer layer, which incorporates traps with defined energy levels and trap densities to optimize switching loss at a given on voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If proton irradiation is used to form a proton donor layer in the N-type buffer layer, then carrier lifetime is controlled and on voltage is reduced, but switching loss increases due to composite defects
Solution Approach 1:
The patent applies parameter changes by precisely controlling the energy level and trap density of defects in the drift layer. Specifically, it introduces three traps at energy levels of 0.246 eV, 0.349 eV, and 0.470 eV below the conduction band, with the second trap having a density of at least 2.0×10^11 cm^-3. This quantitative control of defect parameters enables optimization of both on voltage and switching loss without the harmful effects of composite defects.
2Adaptability or versatility
If different silicon-based semiconductor materials are used, then material properties vary, but trade-off characteristics between on voltage and switching loss become inconsistent
Solution Approach 1:
The patent applies local quality by introducing specific traps with defined energy levels and densities in the drift layer, creating localized defect structures that standardize device characteristics. The presence of three specific traps (at 0.246 eV, 0.349 eV, and 0.470 eV below the conduction band, with the second trap having density ≥2.0×10^11 cm^-3) in the drift layer compensates for variations in silicon-based semiconductor materials, ensuring consistent trade-off characteristics between on voltage and switching loss across different material batches.
3Use of energy by moving object
If composite defects are formed in the proton donor layer, then on voltage increase is suppressed, but switching loss increases and performance consistency deteriorates
Solution Approach 1:
The patent applies the taking out principle by extracting and eliminating composite defects from the system. Instead of allowing composite defects to form in the proton donor layer (which causes increased switching loss), the invention introduces a controlled set of three discrete traps with specific energy levels in the drift layer. This removes the harmful composite defect formation mechanism while maintaining the beneficial carrier lifetime control, thereby suppressing on voltage increase without increasing switching loss.
Data Source
AI summary
A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.0×1011 cm−3.