Drift-Layer Trap Engineering for Stable On-Voltage Switching Trade-Offs
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Solution Overview
Problem
Existing power semiconductor devices face challenges in achieving consistent trade-off characteristics between on voltage and switching loss across different silicon-based semiconductor materials.
Innovation Solution
A semiconductor device is designed with a specific structure, including a semiconductor substrate, a drift layer, an impurity diffusion layer, and a buffer layer, which incorporates traps with defined energy levels and trap densities to optimize switching loss and on voltage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different silicon-based semiconductor materials are used, then material properties vary, but trade-off characteristics between on voltage and switching loss become inconsistent
Solution Approach 1:
The patent applies parameter changes by precisely controlling the energy levels and trap densities of defects in the drift layer. By setting specific trap energy levels (0.246 eV, 0.349 eV, 0.470 eV below conduction band) and trap density (≥2.0×10^11 cm^-3), the invention standardizes the electrical characteristics across different silicon-based materials, ensuring consistent trade-off characteristics between on voltage and switching loss regardless of material variations
Solution Approach 2:
The patent employs composite materials by creating a drift layer with multiple types of traps at different energy levels. The combination of first traps (0.246 eV), second traps (0.349 eV), and third traps (0.470 eV) forms a composite defect structure that collectively controls carrier lifetime and electrical properties, achieving consistent performance across different silicon-based semiconductor materials
Data Source
AI summary
A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.0×1011 cm−3.