Semiconductor Drift Region Doping Layout for Breakdown and ON-Resistance

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Solution Overview

Problem

Existing semiconductor devices struggle to simultaneously increase breakdown voltage and reduce ON-resistance, as uniform n-type impurity concentration in the drift region either increases resistance or decreases breakdown voltage.

Innovation Solution

The semiconductor device incorporates a n−-type drift region with multiple first regions and a second region, where the n-type impurity concentration is higher in the first regions than in the second region, allowing for easier depletion in specific directions while maintaining low resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If uniform n-type impurity concentration is used in the drift region, then manufacturing is simplified, but breakdown voltage decreases and ON-resistance increases

Engineering Contradiction:
Improveimpurity concentration uniformityVSAvoidbreakdown voltage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The drift region is divided into multiple regions with different n-type impurity concentrations: a first region with concentration ND1, a second region with concentration ND2, and a third region with concentration ND3, where ND1 < ND2 < ND3. This local differentiation allows the high-concentration third region to provide low ON-resistance while the low-concentration first region ensures complete depletion and high breakdown voltage, resolving the contradiction between manufacturing simplicity and device performance.

Inventive Principle:
Principle #3Local quality

2Device complexity

If uniform n-type impurity concentration is used in the drift region, then device structure is simplified, but ON-resistance increases

Engineering Contradiction:
Improvedrift region structureVSAvoidON-resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The drift region employs a multi-zone impurity concentration structure with three distinct regions (first, second, and third regions) having progressively increasing n-type impurity concentrations. The third region with the highest concentration (ND3) provides low ON-resistance by facilitating carrier conduction, while the overall graduated structure maintains manageable device complexity through systematic spatial variation rather than uniform composition.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively increases breakdown voltage by ensuring complete depletion of the drift region in critical directions while reducing ON-resistance by optimizing impurity concentration gradients.

Implementation Method 1

a cross section of the n−-type drift region includes a plurality of first regions provided respectively around the plurality of second electrodes in the second direction and the third direction, and a second region provided around the first regions. Impurity concentrations of the first conductivity type in the first regions are higher than an impurity concentration of the first conductivity type in the second region.

Methodology Applied
Scientific EffectImpurity concentration gradient:

Implementation Method 2

This design effectively increases breakdown voltage by ensuring complete depletion of the drift region in critical directions while reducing ON-resistance by optimizing impurity concentration gradients.

Methodology Applied
Scientific EffectDepletion:

Data Source

PatentUS12224345B2Semiconductor device
Publication Date: 2025.02.11 KK TOSHIBA
  • US12224345B2 patent drawing
  • US12224345B2 patent drawing
  • US12224345B2 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.