DRAM Training Acceleration via BIST Hardware
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Solution Overview
Problem
High-speed data processing systems, particularly those using GDDR6 memory, face significant delays during startup and periodic retraining due to the time-consuming process of adjusting timing for each data pin relative to read and write clocks, which negatively impacts user experience.
Innovation Solution
Implementing a built-in self-test (BIST) technique within the memory controller that performs read training by writing a data pattern, determining the edges of the read data eye for each bit lane, and setting corresponding delays, allowing for hardware-based evaluation and reduction of training time by a factor of about 10 with minimal additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional firmware-based training is used, then timing adjustment can be performed, but training time becomes excessively long (several seconds)
Solution Approach 1:
The patent replaces the firmware-based software training mechanism with a hardware-based BIST circuit that performs training operations autonomously. The BIST circuit includes a training sequence generator, data comparison unit, and delay adjustment mechanism that operate in hardware, eliminating the need for firmware loops and significantly reducing training time from several seconds to approximately 0.3 seconds.
Solution Approach 2:
The BIST circuit enables the memory controller to perform self-training without external firmware intervention. The circuit automatically generates training sequences, compares read data against expected values, detects eye diagram edges, and adjusts timing parameters autonomously, making the training process self-contained within the hardware circuitry.
2Reliability
If individual data pin timing adjustment is performed, then data capture reliability is improved, but training complexity increases
Solution Approach 1:
The patent segments the training process into distinct phases: writing data patterns, reading data back, comparing data, detecting edges, and adjusting delays. Each phase is handled by dedicated circuit components within the BIST structure, allowing complex timing adjustment to be broken down into manageable hardware operations that maintain reliability while reducing overall complexity.
Solution Approach 2:
The BIST circuit acts as an intermediary between the memory controller and the memory device, providing a dedicated hardware layer that handles the complex timing adjustment tasks. This intermediary structure isolates the complexity of individual pin timing adjustment from the main system logic, allowing reliable data capture without proportionally increasing system-level complexity.
Data Source
AI summary
A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.