Drive Circuit Aging Using DC Stress for Fault Detection
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Solution Overview
Problem
Existing chip aging methods fail to accurately and efficiently detect row or multi-row failures in chips like DRAM, leading to unreliable computer devices due to undetected faults in drive circuits.
Innovation Solution
A chip aging method and apparatus that applies direct current stress through controlled electric fields and temperature adjustments to accelerate time-dependent dielectric breakdown and hot carrier degradation in drive circuits, ensuring faster and more accurate detection of faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternating current stress is applied to the inverter, then the electric field changes continuously, but the aging acceleration effect is insufficient
Solution Approach 1:
The patent changes the electrical stress parameter from alternating current to direct current, applying a constant voltage level to the inverter input end. This parameter change transforms the electric field from dynamic to static, creating continuous direct current stress that significantly accelerates time-dependent dielectric breakdown and hot carrier degradation, thereby improving both aging detection speed and accuracy
Solution Approach 2:
The patent maintains stable voltage levels at the inverter input end throughout the aging test, ensuring continuous application of direct current stress. This continuous action prevents the electric field from changing or relaxing, maintaining constant acceleration effect on dielectric breakdown and hot carrier degradation processes, thus improving detection efficiency
2Reliability
If conventional aging test methods are used, then the test process is simple, but row or multi-row failures cannot be detected
Solution Approach 1:
The patent applies direct current stress with stable voltage levels to the inverter, creating maximum electric field conditions that accelerate time-dependent dielectric breakdown. This parameter change enables the detection of latent defects in drive circuits that conventional alternating current methods cannot reveal, improving fault detection capability while maintaining test simplicity
Solution Approach 2:
The patent performs preliminary aging acceleration on the drive circuit before final chip testing. By applying direct current stress to accelerate dielectric breakdown and hot carrier degradation in advance, potential faults are revealed early in the testing process, enabling timely detection of row or multi-row failure risks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly accelerates the aging process of drive circuits, identifying potential faults and preventing row or multi-row failures, thereby enhancing the reliability of computer devices by ensuring only functional chips are delivered.
Implementation Method 1
a maximum electric field is formed at a dielectric layer. The maximum electric field can accelerate time-dependent dielectric breakdown at the dielectric layer and accelerate aging of the drive circuit.
Implementation Method 2
Because a reverse level is output due to an inversion function of the inverter, a maximum electric potential difference is formed between the input end and the output end of the inverter
Implementation Method 3
there is a maximum voltage difference between the source and the drain of the selection transistor, and a maximum electric field is formed to accelerate hot carrier degradation, thereby accelerating aging of the drive circuit.
Implementation Method 4
the aging apparatus outputs a first level to the inverter, where the first level is used to form a direct current field between the input end and the output end of the inverter
Data Source
AI summary
An aging apparatus is connected to a drive circuit of a chip, and the drive circuit includes an inverter and at least one selection transistor. The apparatus is connected to an input end of the inverter and a gate of the selection transistor, an output end of the inverter is connected to a drain of the selection transistor, a source of the selection transistor and a second power supply end of the inverter are connected to a low voltage, and a first power supply end of the inverter is connected to a high voltage.