Drive Circuit Aging Using DC Stress for Row Failure Screening
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Solution Overview
Problem
Existing chip aging methods fail to accurately and efficiently stimulate row or multi-row failures in chips like DRAM, leading to unreliable computer devices due to undetected defects.
Innovation Solution
A chip aging method and apparatus that applies direct current stress through controlled electric fields and temperature adjustments to accelerate time-dependent dielectric breakdown and hot carrier degradation in drive circuits, ensuring faster and more accurate detection of faulty components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternating current stress is used to continuously change the level at the input end of the inverter, then the electric field applied to the dielectric layer is changed, but the acceleration effect on time-dependent dielectric breakdown is insufficient
Solution Approach 1:
The patent changes the electrical stress parameter from alternating current to direct current, applying a constant high voltage level to the inverter input end. This parameter change transforms the electric field from dynamic to static, significantly enhancing the acceleration effect on time-dependent dielectric breakdown and improving both detection accuracy and speed.
2Reliability
If conventional aging test methods are used, then the testing process is simple, but row or multi-row failures cannot be stimulated and defective chips enter the market
Solution Approach 1:
The patent modifies the electrical stress parameters by applying direct current with specific voltage levels (first level to form DC field, second level to connect power supply path, third level to form DC field at transistor) to stimulate row or multi-row failures. This parameter optimization enables detection of previously undetected defects while maintaining a relatively simple testing structure.
3Productivity
If direct current stress is applied to the inverter, then time-dependent dielectric breakdown is accelerated, but the testing methodology becomes more complex
Solution Approach 1:
The patent segments the aging test into distinct stages with specific voltage level applications: first level for DC field formation, second level for power supply path connection, and third level for transistor DC field formation. This segmentation organizes the complex direct current stress testing into manageable steps, improving aging acceleration speed while maintaining methodological clarity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly accelerates the aging process of drive circuits, identifying and eliminating potential failures, thereby enhancing the reliability of chips by preventing row or multi-row failures post-delivery.
Implementation Method 1
the level is maintained to be stable, and the input level at the input end of the inverter is not changed. This is equivalent to that an applied electric field is an electric field of a direct current property, that is, a direct current stress. Acceleration effect of the direct current stress on TDDB is greater than that of the alternating current stress.
Implementation Method 2
Because a reverse level is output due to an inversion function of the inverter, a maximum electric potential difference is formed between the input end and the output end of the inverter, that is, a maximum electric field is formed at a dielectric layer.
Implementation Method 3
the acceleration effect of the direct current stress on HCI is greater than that of the alternating current stress, aging of the drive circuit can be further accelerated.
Data Source
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AI summary
A chip aging method and apparatus are provided. The aging apparatus (204) is connected to a drive circuit of a chip, and the drive circuit includes an inverter (N1) and at least one selection transistor. The apparatus is connected to an input end of the inverter (N1) and a gate of the selection transistor, an output end of the inverter (N1) is connected to a drain of the selection transistor, a source of the selection transistor and a second power supply end (Vbb) of the inverter (N1) are connected to a low voltage, and a first power supply end (Vhigh) of the inverter (N1) is connected to a high voltage. The method includes: outputting a first level, used to form a direct current field between an input and an output of the inverter (N1), to the inverter (N1); or outputting a second level, used to control the first power supply end (Vhigh) and the output end to be connected, to the inverter (N1), and outputting a third level, used to form a direct current field between the source and the drain of the selection transistor, to the gate of the selection transistor, so that a drive circuit having a quality problem fails after accelerated aging, thereby avoiding a row or multi-row failure of a chip caused by time-dependent dielectric breakdown or hot carrier degradation of a drive circuit after delivery.