Power Semiconductor Drive Circuit for Asynchronous Error Masking
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Solution Overview
Problem
Conventional drive circuits for power semiconductor elements fail to remove asynchronous error signals, leading to malfunctions due to manufacturing variations and noise-induced recovery currents, despite being capable of handling synchronous error signals.
Innovation Solution
A drive circuit with a level shift circuit, RS flip flops, and a logic filter circuit that blocks signal transmission during specific logic transitions, effectively removing both synchronous and asynchronous error signals by using inverters, NAND, NOR circuits, and RS flip flops to generate a mask signal that prevents erroneous signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the time period during which recovery current flows and the time period during which off signal is generated overlap, then asynchronous error signals are generated due to manufacturing variations, but conventional circuits cannot remove these signals
Solution Approach 1:
The circuit performs preliminary timing analysis by monitoring the overlap between recovery current flow period and off-signal generation period before error signals are generated. The mask signal is prepared in advance to prevent asynchronous error signals from reaching the RS flip-flop, rather than attempting to filter them after generation.
2Reliability
If manufacturing variation causes difference in malfunctioning signal margin between on-signal side and off-signal side elements, then asynchronous error signals occur due to non-coincident rise or fall times, but conventional circuits only handle simultaneous errors
Solution Approach 1:
The circuit uses two separate RS flip-flops to independently handle on-signal and off-signal processing. This segmentation allows each flip-flop to be optimized for its specific signal type and timing characteristics, accommodating manufacturing variations without requiring complex synchronized filtering.
Solution Approach 2:
The circuit employs asymmetric treatment of on-signal and off-signal paths by using different filtering mechanisms: conventional logic filtering for synchronous errors and mask-signal-based timing control for asynchronous errors. This asymmetry allows the circuit to adapt to the different timing characteristics caused by manufacturing variations in each path.
Data Source
AI summary
A drive circuit has a level shift circuit which outputs level-shifted on and off signals each for controlling a power semiconductor element in an on or off state, a first RS flip flop which is supplied with the on signal through a setting input terminal and supplied with the off signal through a resetting input terminal, and which outputs a drive signal to the power semiconductor element, and a logic filter circuit which is provided between the level shift circuit and the first RS flip flop, and which blocks transmission of the on and off signals during the time period from a time at which both the on and off signals become a first logic to a time at which both the on and off signal become a second logic.