Display Driver Circuit Timing for Low-Distortion Pulse Output
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing signal distortion, signal delay, and transistor degradation, while also aiming to decrease channel width, layout area, and display device frame size, while improving display quality and reducing cost.
Innovation Solution
A semiconductor device is designed with a driver circuit comprising multiple pulse output circuits with specific transistor connections and clock signal configurations, allowing for efficient signal processing and reduced signal delay, while also suppressing transistor degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the channel width of transistor is decreased to reduce layout area, then the layout area is reduced, but signal distortion and signal delay increase
Solution Approach 1:
The patent applies parameter changes by adjusting the duty ratio of clock signals supplied to different signal lines. Specifically, the first clock signal has a first duty ratio and the second clock signal has a second duty ratio different from the first. This parameter modification optimizes signal transmission characteristics through the transistor, reducing signal distortion and delay even when the channel width is reduced for smaller layout area.
2Area of stationary object
If the channel width of transistor is decreased to reduce layout area, then the layout area is reduced, but transistor degradation accelerates
Solution Approach 1:
The patent uses parameter changes by varying the duty ratio of clock signals applied to different signal lines. The first clock signal supplied to the first signal line has a first duty ratio, while the second clock signal supplied to the second signal line has a second duty ratio. This differential duty ratio configuration reduces stress on the transistor, suppressing degradation and improving reliability while maintaining a reduced channel width for compact layout area.
3Device complexity
If clock signals with same duty ratio are used to simplify circuit design, then device complexity is reduced, but signal distortion and delay increase
Solution Approach 1:
The patent implements parameter changes by assigning different duty ratios to clock signals on different signal lines. The first clock signal has a first duty ratio and the second clock signal has a second duty ratio, which are optimized to minimize signal distortion and delay. This approach maintains relatively simple circuit design while achieving superior signal transmission performance through careful parameter selection.
4Device complexity
If larger frame size is used to accommodate driver circuit, then device complexity is reduced, but display device size increases
Solution Approach 1:
The patent applies parameter changes by using different duty ratios for clock signals on different signal lines, which optimizes signal transmission efficiency and reduces signal degradation. This enables the driver circuit to be integrated into a compact form factor, reducing the overall frame size of the display device while maintaining circuit functionality and performance.
Data Source
AI summary
One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.