Driver Circuit Signal Level Calibration for Display Uniformity
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Solution Overview
Problem
Existing driver circuits for electro-optical devices face challenges in accurately calibrating signal levels, leading to display unevenness due to variations in output data signal levels, which are difficult to suppress, especially during vertical blanking intervals.
Innovation Solution
A driver circuit that includes data signal output units, a timing signal output unit, a detection unit, an adjustment unit, and a signal control unit to precisely calibrate and adjust signal levels by stopping at least one timing signal before detection, ensuring stable and uniform signal delivery to pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration is performed during vertical blanking interval, then writing operation voltage variation is avoided, but voltage drop occurs and correct output level cannot be detected
Solution Approach 1:
The patent extracts the timing signal from the calibration process by stopping it during detection. This isolates the detection phase from the influence of timing signals, allowing accurate measurement of output levels without the interference that causes voltage drops and detection failures.
Solution Approach 2:
The patent performs preliminary action by stopping the timing signal before detection begins. This preparatory step ensures that no voltage drop occurs during the measurement process, guaranteeing that the detected output level reflects the true signal level without interference from active timing signals.
2Productivity
If data signal is divided and provided by multiple output units, then writing time into pixels is sufficient, but signal level variation occurs causing display unevenness
Solution Approach 1:
The patent implements feedback by detecting the actual output levels from each data signal output unit and using this information to adjust their respective signal levels. This closed-loop control ensures that all output units maintain uniform signal levels despite variations in their output characteristics, eliminating display unevenness while preserving high-speed parallel writing capability.
Solution Approach 2:
The patent changes the signal level parameter of each output unit based on detected variations. By adjusting the output levels of individual units to compensate for their characteristic differences, the system achieves uniform signal levels across all pixels while maintaining the high productivity benefits of parallel data signal division.
3Reliability
If timing signal is active during detection, then normal operation is maintained, but voltage drop occurs and signal level detection becomes inaccurate
Solution Approach 1:
The patent extracts the timing signal from the detection phase by stopping it temporarily. This separation allows the detection process to occur in isolation from the timing signal's influence, eliminating voltage drops and ensuring accurate signal level measurement while maintaining normal operation continuity through subsequent resumption of the timing signal.
Solution Approach 2:
The patent performs the preliminary action of stopping the timing signal before detection begins. This ensures that the detection process occurs under stable voltage conditions without the interference of active timing signals, guaranteeing measurement accuracy while allowing normal operation to resume immediately after detection completes.
Data Source
AI summary
A driver circuit includes a plurality of data signal output units each configured to provide the electro-optical device with the data signal, a timing signal output unit configured to provide the electro-optical device with the timing signals, a detection unit configured to detect signal levels of the data signals provided by the data signal output units, an adjustment unit configured to adjust the signal levels of the data signals provided by the data signal output units so as to approach one another on the basis of the detected signal levels, and a signal control unit configured to control the timing signal output unit so as to stop at least one of the timing signals before the detection unit detects the signal level.