Driver Circuit Transistor Deterioration Suppression
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Solution Overview
Problem
Existing driver circuits for liquid crystal display devices using non-single-crystal semiconductors face issues such as increased threshold voltage, decreased mobility, high parasitic capacitance, and large layout area, leading to shortened lifespan, increased power consumption, and potential short circuits.
Innovation Solution
The proposed solution involves a driver circuit configuration with a reduced number of transistors connected to a capacitor, decreased parasitic capacitance, and optimized signal potential levels, which helps in reducing the layout area, extending the circuit's lifespan, and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the other electrode of the capacitor is connected to the gates of two transistors, then the potential of the other electrode is increased or decreased by making the potential synchronize with the clock signal, but the parasitic capacitance of a node connected to the capacitor becomes high
Solution Approach 1:
The patent extracts the capacitor's other electrode connection from the gate nodes of transistors and relocates it to a dedicated wiring that does not connect to transistor gates. This separation removes the source of high parasitic capacitance while preserving the capacitor's ability to synchronize potential with the clock signal through the isolated wiring connection.
2Reliability
If the parasitic capacitance of a node connected to the capacitor is high, then the capacitance value of the capacitor should be large, but the area where the one electrode and the other electrode of the capacitor overlap needs to be large
Solution Approach 1:
The patent extracts the capacitor's other electrode connection from transistor gates and connects it to a separate wiring, which reduces the number of transistors that need to be connected to the capacitor. This reduction decreases the required capacitor value and consequently reduces the overlap area between capacitor electrodes, allowing for a more compact layout.
3Object-generated harmful factors
If the number of transistors connected to a capacitor is reduced, then the parasitic capacitance decreases, but the circuit complexity may increase
Solution Approach 1:
The patent makes the wiring connected to the capacitor's other electrode serve multiple functions: it acts as both a signal transmission line and a connection point for the capacitor. This multi-functionality reduces the need for separate dedicated connections, thereby reducing the number of transistors that need to be connected to the capacitor while avoiding increased circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses transistor deterioration, reduces signal delay and distortion, decreases power consumption, and prevents short circuits, thereby enhancing the reliability and efficiency of the driver circuit.
Implementation Method 1
by utilizing capacitive coupling of the capacitor, signals that synchronize with the clock signal are generated in the gates of the two transistors
Data Source
AI summary
It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.