High-Speed Driver Equalization With De-Emphasis for ISI Reduction
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Solution Overview
Problem
Current driver equalization designs for high-speed serial data transmission over copper lines are complex and costly, leading to increased manufacturing expenses and inefficiencies in reducing inter-symbol interference.
Innovation Solution
A simplified digital filter approach using a de-emphasis circuit with a main analog driver and a de-emphasis driver that delays and inverts the data signal, applying additive or subtractive effects based on bit values to achieve signal pre-emphasis or de-emphasis while maintaining constant output impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex digital filter designs are used for driver equalization, then inter-symbol interference is reduced, but manufacturing costs increase substantially
Solution Approach 1:
The complex digital filter is segmented into multiple simple delay elements (D1, D2, D3, D4) and basic logic gates. Each delay element processes a portion of the signal with a specific delay time, and the results are combined through simple logic operations. This segmentation transforms a complex manufacturing problem into multiple simple, standardized components that are easier and cheaper to manufacture while achieving the same equalization effect.
Solution Approach 2:
The patent uses multiple identical delay elements (D1-D4) that are simple copies of each other, rather than implementing a complex unique filter structure. These copied delay elements can be manufactured using standard delay circuit blocks, reducing manufacturing complexity and cost while maintaining the required signal processing functionality through their collective arrangement.
2Reliability
If driver equalization is applied to reduce inter-symbol interference, then signal quality improves, but device complexity increases
Solution Approach 1:
The equalization function is segmented into discrete delay stages (D1-D4) with specific delay times (T1-T4). Each stage processes the signal independently with a simple delay operation, avoiding the need for a complex monolithic filter design. The segmented approach maintains signal quality through cumulative delay effects while keeping individual components simple.
Solution Approach 2:
The delay elements are configured to perform preliminary signal processing before the main signal combination. By pre-delaying the signal portions in controlled stages, the system prepares the signal in advance for the final equalization operation, simplifying the overall device structure compared to performing all processing in a complex real-time filter.
3Reliability
If de-emphasis is applied to subsequent bits, then amplitude equalization is achieved, but output impedance varies
Solution Approach 1:
The patent carefully controls the delay parameters (T1, T2, T3, T4) and weighting factors (k1, k2, k3, k4) to achieve amplitude equalization while maintaining impedance stability. By adjusting these parameters within specific ranges, the system achieves the desired de-emphasis effect on subsequent bits while keeping the overall output impedance approximately constant, resolving the contradiction between amplitude equalization and impedance stability.
Data Source
AI summary
The present invention relates to emphasizing and de-emphasizing of an analog data signal. Using a main analog driver a data signal indicative of bit values of binary data is converted into a first analog data signal. A second data signal is determined by delaying the data signal a predetermined time interval and inverting the delayed data signal. Using a de-emphasis driver, the second data signal are converted into a second analog data signal, wherein the second analog data signal is additive to the first analog data signal if the data signal and the second data signal are indicative of a same bit value, and wherein the second analog data signal is subtractive to the first analog data signal if the data signal and the second data signal are indicative of an opposite bit value. The first analog data signal is emphasized or de-emphasized by superposing the first analog data signal and the second analog data signal.