Driver IC Pin Group Layout for Flat Panel Power Drop Reduction
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Solution Overview
Problem
In conventional flat panel displays, the long transmission paths for power signals and gamma voltage to the tailmost driver IC chips result in significant power drops, affecting the output of these chips.
Innovation Solution
The driver IC chips are designed with a configuration where the second pin group is located at least one or two opposite sides of the first pin group, which is electrically coupled to the fan-out wiring areas, reducing excessive transmission path lengths and thus alleviating power drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If driver IC chips are placed at the periphery of the display substrate, then the display area can be maximized, but the transmission path length for power signals and gamma voltage becomes excessively long causing significant power drops
Solution Approach 1:
The driver IC chip is divided into two separate pin groups (first pin group and second pin group) located at opposite ends of the chip. This segmentation allows power signals and gamma voltage to be supplied to different regions of the chip through separate pathways, reducing the effective transmission distance for each signal type and minimizing power drops while maintaining the peripheral placement configuration.
2Reliability
If the transmission path length is reduced to minimize power drops, then the output performance of driver IC chips is improved, but the layout flexibility and display area utilization are constrained
Solution Approach 1:
The pin groups are positioned asymmetrically at opposite ends of the driver IC chip rather than being centrally located or symmetrically distributed. This asymmetric arrangement optimizes the transmission paths for power and gamma voltage signals by directing them through different routes, reducing interference and power drops while maintaining layout flexibility for various display configurations.
Data Source
AI summary
A driver integrated circuit chip adapted to electrically couple with a fan-out wiring area includes a side and a plurality of output pins formed at the side. The output pins includes a first pin group and a second pin group. The first pin group is electrically coupled to the fan-out wiring area. The second pin group is located at at least one side of the first pin group and opened. The present invention also provides display substrates of flat panel display each adapted to electrically couple with a plurality of driver integrated circuit chips.