Driving Backplane Layout for High-Density Narrow-Bezel Displays
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Solution Overview
Problem
Current display technologies face challenges in achieving high pixel density and efficient design for narrow bezels due to limited space for pixel driving circuits, which affects manufacturing and display quality.
Innovation Solution
A driving backplane design with a specific arrangement of data lines, gate lines, and pixel driving circuits, including transistors and storage capacitors, that allows for efficient use of space by sharing conductive portions and electrodes, and utilizing insulating layers with via holes for connections, enabling high pixel density without overlapping gate lines and contact portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel density is increased to improve display quality, then the number of pixels per inch increases, but the available space for pixel driving circuits decreases
Solution Approach 1:
The patent merges the gate driver circuit with the pixel driving circuit by sharing the same active layer and conductive portions. Specifically, the first transistor's active layer serves dual purposes: as the pixel driving transistor and as part of the gate driver circuit, eliminating the need for separate circuit areas and enabling higher pixel density.
Solution Approach 2:
The active layer is designed with multi-functionality, where the same active layer and conductive portions perform multiple functions. The first transistor's conductive portion acts as both a pixel driving element and a gate driver output, allowing one structure to serve multiple purposes and reduce overall circuit area.
2Area of stationary object
If pixel driving circuits are integrated to save space, then area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the active layer into distinct functional regions (active portion, first conductive portion, second conductive portion) that can be independently controlled through different gate lines. This segmentation allows complex functions to be achieved through simple structural divisions, maintaining manufacturing ease while enabling high integration.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking multiple insulating layers and via holes to connect different circuit levels. This three-dimensional arrangement allows complex circuit interconnections to be achieved without increasing planar area, and the layered structure follows standard semiconductor manufacturing processes.
3Area of stationary object
If shared conductive portions are used to reduce area, then space efficiency improves, but signal transmission reliability may be affected
Solution Approach 1:
The patent applies different quality characteristics to different portions of the shared active layer. The active portion has optimized properties for pixel driving, while the first conductive portion is optimized for gate driver signal transmission. This local optimization ensures that each function performs reliably even though they share the same physical structure.
Solution Approach 2:
The insulating layers with precisely positioned via holes act as intermediaries that connect different circuit elements through the shared conductive portions. These intermediary structures ensure proper electrical isolation and connection, maintaining signal transmission reliability while enabling space-efficient sharing of conductive portions.
Data Source
AI summary
A driving backplane includes a base substrate, and data lines, a first gate line, a second gate line and pixel driving circuits that are disposed on the base substrate. The first gate line and the second gate line are adjacent. Each pixel driving circuit includes a first transistor including an active layer. The active layer includes an active portion, a first conductive portion and a second conductive portion. Active portions of first transistors further include first contact portions. The pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit that are coupled to a data line and the first gate line. A first conductive portion in the first pixel driving circuit and a first conductive portion in the second pixel driving circuit are in contact through a first contact portion, and are coupled to the data line through the first contact portion.