Driving Chip Bump Layout for Early Display Defect Detection
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Solution Overview
Problem
Display devices suffer from defects that reduce their performance and reliability, particularly in the driving chips, which are critical for image display.
Innovation Solution
The display device incorporates a driving chip with dummy bumps and detection bumps that are connected in parallel to output bumps, allowing for the detection of defects by measuring the waveform or level of control signals or voltages applied to the output bumps, thereby delaying the occurrence of defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy bumps and detection bumps are added to the driving chip, then reliability is improved through defect detection capability, but device complexity increases due to additional bump structures and connection lines
Solution Approach 1:
The driving chip's bump structure is segmented into three distinct functional types: output bumps for signal transmission, detection bumps for defect monitoring, and dummy bumps for redundancy. This segmentation allows each bump type to perform its specific function independently, enabling defect detection without compromising the overall chip functionality.
Solution Approach 2:
The detection bumps are configured to preliminarily detect potential defects in the driving chip before they manifest as actual failures. By continuously monitoring the electrical characteristics of output bumps through detection bumps, the system can identify and address issues early, preventing complete chip failure.
2Measurement precision
If multiple detection bumps are implemented across different rows, then measurement precision is improved for defect detection, but device complexity increases due to additional connection lines and transistors
Solution Approach 1:
The detection bumps are segmented and arranged in multiple rows corresponding to different output bump rows. Each detection row independently monitors its corresponding output row, allowing precise localization of defects to specific chip regions. This spatial segmentation enables accurate defect detection while maintaining manageable connection line complexity through organized routing.
Solution Approach 2:
Switching transistors are introduced as intermediary components between the detection bumps and output bumps. These transistors act as controlled connection points, allowing the detection circuitry to selectively connect to and monitor different output bumps. This intermediary mechanism enables precise defect detection across multiple rows without requiring permanent, complex direct connections between all detection and output elements.
3Reliability
If dummy bumps are attached to the driving chip, then reliability is improved through redundancy, but manufacturing precision requirements increase due to precise alignment needs
Solution Approach 1:
The dummy bumps are merged with the output bumps and detection bumps to form a unified bump array structure. All three bump types share the same attachment surface on the driving chip and are subjected to the same bonding process. This merging approach allows the use of common alignment reference marks and bonding fixtures, reducing the overall manufacturing precision requirements compared to treating dummy bumps as separate, independently aligned components.
Solution Approach 2:
The dummy bumps are strategically positioned in specific locations within the bump array, particularly in regions where redundancy is most beneficial. By concentrating dummy bumps in key areas rather than uniformly distributing them, the design achieves reliable redundancy while minimizing the total number of bumps that require precise alignment, thereby reducing overall manufacturing complexity.
Data Source
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AI summary
A display device includes: a substrate including a display area and a non-display area positioned around the display area and including a pad area adjacent to one side of the display area, a light emitting element disposed in the display area on the substrate, a pad portion disposed in the pad area on the substrate and including a plurality of output pads, a driving chip, and a control signal line. The driving chip includes a base portion facing the substrate, overlapping the pad area, and including dummy bump areas, an output bump area positioned between the dummy bump areas, and a data output area positioned between the dummy bump areas, a plurality of dummy bumps attached to a lower surface of the base portion and overlapping the dummy bump areas and the output bump area, respectively, a plurality of output bumps attached to the lower surface of the base portion, overlapping the output bump area, and connected in parallel to each other through transistors, and a plurality of detection bumps attached to the lower surface of the base portion, each of the detection bumps is electrically connected to the output bumps and overlapping the output bump area. The control signal line electrically connected through the transistors to the output bumps.