Driving Circuit Level Conversion for Display Timing Controller Compatibility
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Solution Overview
Problem
The existing display technology faces a challenge in matching a single timing controller with different gate driving chips due to signal level compatibility issues, leading to increased production costs and material usage from requiring multiple circuit board designs.
Innovation Solution
A driving circuit with an input module and an output module, utilizing transistors of different types (P-type and N-type) to input and output level signals, allowing the timing controller to generate accurate control signals compatible with various gate driving chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different types of gate driving chips use different signal levels, then each gate driving chip can operate with its optimal signal level, but the timing controller cannot be directly matched with different types of gate driving chips, requiring different versions of circuit boards
Solution Approach 1:
The patent introduces a level conversion circuit as an intermediary component between the timing controller and gate driving chips. This circuit converts signal levels between different standards (e.g., 5V to 3.3V), enabling the timing controller to communicate with various types of gate driving chips without requiring different circuit board versions. The intermediary circuit resolves the incompatibility issue while maintaining a unified circuit board design.
Solution Approach 2:
The patent changes the signal level parameter dynamically based on the connected gate driving chip type. The level conversion circuit detects or is configured to output appropriate signal levels (5V or 3.3V) as needed, allowing a single timing controller to adapt to different chip requirements. This parameter adjustment enables universal compatibility without increasing circuit board versions.
2Reliability
If different versions of circuit boards are designed to match different gate driving chips, then signal compatibility is achieved, but production costs and material usage increase
Solution Approach 1:
The patent makes the circuit board universal by incorporating a level conversion circuit that can handle multiple signal level standards. This single circuit board design serves multiple functions by supporting both 5V and 3.3V gate driving chips, eliminating the need for different board versions. The universal design reduces raw material consumption while maintaining signal compatibility through the adaptive level conversion capability.
3Reliability
If different versions of circuit boards are designed to match different gate driving chips, then signal compatibility is achieved, but production costs increase
Solution Approach 1:
The circuit board is designed with universal compatibility through the inclusion of a level conversion circuit, allowing a single design to support multiple gate driving chip types. This eliminates the need for maintaining multiple board versions in production, reducing manufacturing complexity and costs while ensuring signal compatibility through automated level conversion.
Solution Approach 2:
The level conversion circuit acts as a mediator that resolves signal level incompatibilities without requiring different circuit board versions. By incorporating this intermediary component, the system achieves signal compatibility for various chip types using a unified board design, simplifying production and reducing costs associated with manufacturing and inventorying multiple board variants.
Data Source
AI summary
The present disclosure discloses a driving circuit and a display device. The driving circuit of the present disclosure inputs a level signal to a first node under the control of a first signal control terminal and a second signal control terminal, and then outputs a signal of a first power supply terminal or a second power supply terminal to the output terminal under the control of the level signal of the first node, so as to output different level signals under the control of two the control signals, thereby resolving a problem that one timing controller cannot be directly matched with different gate driving chips in use.