Driving Circuit for Display Devices Using Multi-Phase Clock Signals
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Solution Overview
Problem
Display devices using a clock with more phases experience instability in scanning signals, leading to potential leakage and decreased display quality due to reduced charging opportunities for nodes in the driving circuit.
Innovation Solution
The driving circuit incorporates multiple output circuits with transistors and charging lines equipped with rectifying elements to maintain active potential at nodes, utilizing a clock signal with multiple phases to ensure stable scanning signal output by optimizing charging timings and connections between clock and scanning signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a clock signal with more phases is used to lower the frequency, then the number of charging and discharging cycles of the transistor is decreased, but the charging opportunities for the node are reduced causing potential to be lost
Solution Approach 1:
The patent applies preliminary action by introducing a first charging line that charges the second node in advance during a first time period before the main output operation. This preliminary charging ensures that even when using a multi-phase clock with lower frequency, the node maintains sufficient potential without requiring frequent charging cycles during the output phase.
Solution Approach 2:
The patent segments the charging function into two distinct charging lines with different timing functions. The first charging line handles preliminary charging during a first time period, while the second charging line handles charging during a second time period. This segmentation allows the system to maintain node potential with fewer charging opportunities by distributing the charging function across different time periods.
2Duration of action of moving object
If the frequency of the clock signal is lowered by using more phases, then transistor wear is reduced, but the stability of scanning signal output deteriorates due to insufficient charging opportunities
Solution Approach 1:
The first charging line performs preliminary charging of the second node during a first time period that is established before the main scanning signal output. This preliminary action ensures that the node is ready with sufficient potential when the scanning signal needs to be output, maintaining signal stability even with extended clock periods.
Solution Approach 2:
The patent ensures continuous potential maintenance by providing multiple charging opportunities through different charging lines at different times. The first charging line charges during a first time period and the second charging line charges during a second time period, creating continuous charging action that maintains node potential throughout the extended clock cycle.
3Device complexity
If a single charging line is used to maintain node potential, then the circuit complexity is reduced, but the ability to maintain potential with lower frequency clocks deteriorates
Solution Approach 1:
The patent segments the charging function into two independent charging lines, each responsible for charging during specific time periods. This segmentation allows the system to maintain node potential more reliably with lower frequency clocks by distributing the charging burden across different time periods rather than relying on a single charging line to handle all charging needs.
Solution Approach 2:
The first charging line is specifically designed to perform preliminary charging during a first time period before the main output operation. This preliminary action ensures that the node is pre-charged with sufficient potential, allowing the system to operate reliably with extended clock periods where a single charging line would be insufficient.
Data Source
AI summary
In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.