Driving Circuit With Resistors To Suppress Through Current
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Solution Overview
Problem
Conventional driving circuits for power switching elements face reliability issues due to through currents flowing through p-channel and n-channel transistors during overlap periods, leading to reduced reliability and increased heat generation.
Innovation Solution
A driving circuit incorporating a first switching element, a second switching element, and a current suppressing element that alternately sets charging and discharging lines conductive to supply and discharge charges to the power switching element, with resistors connected in series with the transistors to suppress through currents, thereby reducing heat generation and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p-channel and n-channel transistors are turned on in synchronization with leading and trailing edges of output pulse, then the driving circuit can supply and discharge electric charge to the gate of power switching element, but through current flows through both transistors during overlap period, lowering reliability
Solution Approach 1:
The patent introduces a delay circuit that delays the turn-on timing of the p-channel transistor relative to the n-channel transistor. This preliminary timing adjustment prevents the overlap period where both transistors are simultaneously on, thereby eliminating the through current path and improving reliability without sacrificing the charge supply function to the gate.
2Productivity
If through current flows through conducting elements during overlap period, then switching operation can be performed, but heat generation increases and reliability is lowered
Solution Approach 1:
By using the delay circuit to preliminarily adjust the timing sequence, the patent eliminates the overlap period that causes through current and heat generation, while maintaining the ability to perform switching operations through the alternation of charge supply and discharge phases.
3Ease of operation
If charging line and discharging line are set conductive alternately, then positive and negative voltage can be applied to gate, but overlap period causes through current to flow
Solution Approach 1:
The delay circuit performs a preliminary timing adjustment that sequences the activation of charging and discharging lines to prevent their simultaneous conduction, thereby eliminating the through current path while preserving the alternating voltage application capability to the gate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses through currents, enhancing the reliability and efficiency of the power switching operation by adjusting the charging and discharging speeds while minimizing heat generation and noise, allowing for stable high-frequency switching.
Implementation Method 1
a first switching element sets a charging line at a conductive state in response to a first edge of an output pulse to supply an electric charge to a conducting control terminal of a power switching element through the first switching element and the charging line
Implementation Method 2
a second switching element sets a discharging line at a conductive state in response to a second edge of the output pulse to discharge the supplied electric charge from the conducting control terminal of the power switching element through the second switching element and the discharging line
Implementation Method 3
The current suppressing element suppresses a through current flowing, in response to at least one of the first and second edges of the output pulse, through the first switching element and the second switching element
Data Source
AI summary
A driving circuit has a p-channel transistor and an n-channel transistor. A power switching element is set at an on state each time the p-channel transistor sets a charging line at a conductive state in response to a leading edge of an output pulse to supply a positive charge to a gate of the element through the charging line. The element is set at an off state each time the n-channel transistor sets a discharging line at a conductive state in response to a trailing edge of the output pulse to discharge the supplied charge through the discharging line. A through current occasionally flows through the transistors set at the on state together. The driving circuit has resistors between the transistors to suppress the through current.