Driving Circuit Adjusting Output Timing for Display Panels
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Solution Overview
Problem
Large display panels with high-speed driving schemes experience signal delays in gate signal delivery, leading to non-uniform display quality due to varying charge rates of liquid crystal capacitors near and distant from the gate driver.
Innovation Solution
A driving circuit with a receiver to separate data and clock signals, a clock recovery unit generating multi-phase clock signals, and an output clock generation unit synchronizing data driving signals with the clock and multi-phase signals, adjusting output timing based on data line positions to compensate for signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed driving scheme is employed, then productivity is improved, but signal delay occurs on gate signal delivery path
Solution Approach 1:
The patent applies preliminary action by adjusting the output timing of data driving signals in advance based on the position of data lines. The driving circuit pre-compensates for the gate signal delay by advancing or delaying data signal output timing for different data line groups, ensuring that liquid crystal capacitors at all positions receive properly timed signals despite the inherent gate signal propagation delays in high-speed driving schemes.
2Area of stationary object
If display panel size becomes large, then area increases, but signal delay varies across different positions
Solution Approach 1:
The patent implements local quality by dividing data lines into multiple groups and applying different output timing adjustments to each group based on its position within the display panel. The driving circuit assigns different timing characteristics to data lines at different locations, compensating for the varying signal delays caused by the large panel size and ensuring uniform display quality across the entire display area.
3Speed
If gate signal delivery is optimized, then speed increases, but charge rate uniformity deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the output timing parameter of data driving signals based on data line position. The driving circuit modifies the timing parameters for different data line groups to compensate for gate signal delivery variations, maintaining uniform charge rates across all liquid crystal capacitors even when operating at high gate signal speeds that would otherwise cause non-uniform charging.
Data Source
AI summary
A driving circuit includes a receiver configured to receive an image control signal comprising a data signal and a clock signal, separate the data signal from the clock signal and output the separated data and clock signals, a clock recovery unit generating a reference clock signal based on the clock signal and generating a plurality of multi-phase clock signals having different phases from that of the reference clock signal, an output clock generation unit outputting an output clock signal in synchronization with the clock signal and the plurality of multi-phase clock signals, and a data output unit driving a plurality of data lines with a data driving signal corresponding to the data signal in synchronization with the output clock signal, and the output clock generation unit outputs the plurality of multi-phase clock signals.