Driving Voltage Provider Dynamic Frequency Control
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Solution Overview
Problem
Conventional driving voltage providers consume constant control power and experience thermal stress even when the load decreases, as they operate at a fixed frequency regardless of load fluctuations.
Innovation Solution
A driving voltage provider system that includes a phase-locked loop (PLL) circuit, a DC-DC converter, and tuning circuits to dynamically adjust the divider value based on sampling signals, reducing the frequency of clock signals when the load decreases, thereby reducing control power consumption and thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the driving voltage provider operates at a fixed frequency regardless of load fluctuations, then the clock signal frequency remains stable, but control power consumption increases and thermal stress occurs when load decreases
Solution Approach 1:
The patent implements dynamic frequency adjustment by modifying the fixed operating frequency to become variable based on load conditions. The driving voltage provider continuously monitors load status and adjusts the clock signal frequency accordingly, transitioning from a static to a dynamic operating mode that optimizes power consumption while maintaining stability when needed.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal from a constant value to a variable value that adapts to load conditions. By modifying this key parameter dynamically, the system achieves lower power consumption during light loads while maintaining adequate performance during heavy loads, directly addressing the power consumption issue.
2Device complexity
If the driving voltage provider operates at a fixed frequency regardless of load fluctuations, then the control logic remains simple, but thermal stress increases when load decreases
Solution Approach 1:
The system transitions from static frequency operation to dynamic frequency adjustment, allowing the operating parameters to change based on thermal and load conditions. This dynamic adaptation reduces thermal stress by lowering frequency during light loads while maintaining simplicity through automated control mechanisms.
Solution Approach 2:
The patent implements a feedback mechanism that monitors load conditions and thermal status, then adjusts the clock frequency accordingly. This closed-loop control automatically reduces frequency when thermal stress is detected, eliminating the need for complex manual intervention while managing thermal conditions effectively.
3Use of energy by moving object
If the driving voltage provider reduces clock signal frequency when load decreases, then control power consumption decreases, but frequency stability is compromised
Solution Approach 1:
The system employs dynamic frequency adjustment that adapts to load conditions, allowing frequency to change from fixed to variable. This dynamic approach optimizes power consumption by reducing frequency during light loads while maintaining system stability through controlled transition mechanisms.
Solution Approach 2:
The patent modifies the frequency parameter from constant to variable based on operational needs. By implementing controlled parameter changes rather than arbitrary adjustments, the system achieves power savings while maintaining adequate frequency stability for proper operation.
Data Source
AI summary
A driving voltage provider includes: a PLL circuit for generating clock signals with different phases according to a divider value; a DC-DC converter for generating a PWM signal according to the frequency of a first clock signal, and providing a driving voltage based on the duty ratio of the PWM signal; a first tuning circuit for outputting a first tuning signal having a first logic level when the logic levels of first and second sampling signals obtained by sampling the PWM signal at transition times of different clock signals are different, and outputting the first tuning signal having a second logic level when the first and second sampling signals have the same logic level; and a divider value determiner for decreasing the divider value when the logic level of the first tuning signal is the first logic level.